| Message ID | 20231009082450.452877-1-amelie.delaunay@foss.st.com |
|---|---|
| State | New |
| Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org>
Delivered-To: ouuuleilei@gmail.com
Received: by 2002:a59:a888:0:b0:403:3b70:6f57 with SMTP id x8csp1722007vqo;
Mon, 9 Oct 2023 01:27:09 -0700 (PDT)
X-Google-Smtp-Source:
AGHT+IF6RWNbZ8blvBVo2o/dVtG4OhvkLEQs4e8BDiG10WMNMlLRj8IDG7ebRJC26YvRixrKx+Ju
X-Received: by 2002:a05:6870:c0cd:b0:1e1:e1af:dc3a with SMTP id
e13-20020a056870c0cd00b001e1e1afdc3amr15695311oad.2.1696840028777;
Mon, 09 Oct 2023 01:27:08 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1696840028; cv=none;
d=google.com; s=arc-20160816;
b=PUu+AUymmzsZ1dfhW5mIl+dwDUUlLksrzYITFxwBhjOA+scMEwkpxJMIVnaBIl8Fpy
ONXzQpjzFlBBopuSTYHEV2C6ejG6gxf2fKuog67fHMBMmAacZebqCV2a+8HMgfIUUuqt
poTW1fiePTUM+JSJeMSTPwSvgJSzKLPKhZcnym7K0D2bc+smRMnG0BLeVnKWgovGDgPK
GPT7dVOuzKD1xnH4xFW3XQKNsGOkJyFvilXXNRZ4L67f3XaBml8O1sgbDKixnp0Dtk5U
LCVnwRkVsLf6TzaAMTz0dDoRrwLs+vsiVHIc9M2/psaQYBDDydq6ZEzupGa2KhViFe9S
HeLA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
s=arc-20160816;
h=list-id:precedence:content-transfer-encoding:mime-version
:message-id:date:subject:cc:to:from:dkim-signature;
bh=YAiMtH1WN1ZSofJZ2d2JMLIB05s+WCXSQFpdn3fuvVU=;
fh=qPYd13lMymVBYy12JpDklGTNobmigCjKMFwrrKn5Yk4=;
b=mATEFCkK4cbZ6hxavQLm/e2drhzvWXNGC9gwuWj/up0DTuWJtIJ1NN4WRpgXNAKoEL
bXjxgoouWLvc9pebnYzpUbjRZUVxNeqlmdl41LZ7bnp7YIx1y/JUpz04DCtgS4kOKi+m
uA8YS7oMQASM8GBBwx2m+ZST8x6xT9QdI7AQRNVmxirLdJ2Qs4ny7SH9+bMw+7UJLQQp
J2IGtyWDrJ5uSLrMc1eqeLRnLr9XtkT+MdbWaGH9cAcW6taUCy3M6dUmmn7Ie2RIG5us
X1f6yYTlA21dbnTL17e80b2Nss8r30Dt/BQgGdIvLVRfJYrgQq7PmmNNNcD/dSJZWdVn
eRBA==
ARC-Authentication-Results: i=1; mx.google.com;
dkim=pass header.i=@foss.st.com header.s=selector1 header.b=HzWTIyYj;
spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::3:6 as permitted sender)
smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com
Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6])
by mx.google.com with ESMTPS id
l125-20020a633e83000000b00578b8016c40si9743491pga.93.2023.10.09.01.27.08
(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
Mon, 09 Oct 2023 01:27:08 -0700 (PDT)
Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::3:6 as permitted sender)
client-ip=2620:137:e000::3:6;
Authentication-Results: mx.google.com;
dkim=pass header.i=@foss.st.com header.s=selector1 header.b=HzWTIyYj;
spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::3:6 as permitted sender)
smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com
Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0])
by pete.vger.email (Postfix) with ESMTP id 06503808BE5D;
Mon, 9 Oct 2023 01:26:05 -0700 (PDT)
X-Virus-Status: Clean
X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S234409AbjJIIZq (ORCPT <rfc822;ezelljr.billy@gmail.com>
+ 18 others); Mon, 9 Oct 2023 04:25:46 -0400
Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56484 "EHLO
lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
with ESMTP id S234375AbjJIIZn (ORCPT
<rfc822;linux-kernel@vger.kernel.org>);
Mon, 9 Oct 2023 04:25:43 -0400
Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com
[185.132.182.106])
by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DF1AA6;
Mon, 9 Oct 2023 01:25:41 -0700 (PDT)
Received: from pps.filterd (m0288072.ppops.net [127.0.0.1])
by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id
3997fCIn001364;
Mon, 9 Oct 2023 10:24:54 +0200
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=
from:to:cc:subject:date:message-id:mime-version
:content-transfer-encoding:content-type; s=selector1; bh=YAiMtH1
WN1ZSofJZ2d2JMLIB05s+WCXSQFpdn3fuvVU=; b=HzWTIyYjSLBMvi4XTl2KnnL
SmhhoBF3o9/3b+si7Ya8bSxPUjQkSutp57DRKO/OWwTSgSF87GFB9ZHwmTu6i44D
YPS9EUB8Ee6MJDRhPPGFNWoOs74MZHGngGbhFophPS3zh6TQuIR/mmIpevlFKglf
5LBP4+eb09nqSVGqhzyzJi9lAMpmyqiCAgmeK3MkS04JMPAP0mP1SNe0s90518XL
cmqZxiT+Y5dAFT/RZHtYH1ampsTebk11tteLKNu0RgJdHIDiQdfbRMJL+bUm5Ozm
+JoY5JIP3d1+30fv0eb5bZPblDMf/o3bpHPDuA60JbnB0A7WZGu+oZNNNnPRqIg=
=
Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])
by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tkhg5v22x-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256
verify=NOT);
Mon, 09 Oct 2023 10:24:54 +0200 (MEST)
Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20])
by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A60CC10006B;
Mon, 9 Oct 2023 10:24:51 +0200 (CEST)
Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71])
by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id
9CE582194DE;
Mon, 9 Oct 2023 10:24:51 +0200 (CEST)
Received: from localhost (10.201.20.208) by SHFDAG1NODE3.st.com (10.75.129.71)
with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 9 Oct
2023 10:24:51 +0200
From: Amelie Delaunay <amelie.delaunay@foss.st.com>
To: Vinod Koul <vkoul@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
M'boumba Cedric Madianga <cedric.madianga@gmail.com>,
Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
CC: Alain Volmat <alain.volmat@foss.st.com>,
Amelie Delaunay <amelie.delaunay@foss.st.com>,
<stable@vger.kernel.org>, <dmaengine@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH] dmaengine: stm32-mdma: correct desc prep when channel running
Date: Mon, 9 Oct 2023 10:24:50 +0200
Message-ID: <20231009082450.452877-1-amelie.delaunay@foss.st.com>
X-Mailer: git-send-email 2.25.1
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Originating-IP: [10.201.20.208]
X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com
(10.75.129.71)
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26
definitions=2023-10-09_07,2023-10-06_01,2023-05-22_02
X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,
DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,
RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no
version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test,
not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]);
Mon, 09 Oct 2023 01:26:05 -0700 (PDT)
X-Spam-Level: **
X-getmail-retrieved-from-mailbox: INBOX
X-GMAIL-THRID: 1779265729984041578
X-GMAIL-MSGID: 1779265729984041578
|
| Series |
dmaengine: stm32-mdma: correct desc prep when channel running
|
|
Commit Message
Amelie Delaunay
Oct. 9, 2023, 8:24 a.m. UTC
From: Alain Volmat <alain.volmat@foss.st.com> In case of the prep descriptor while the channel is already running, the CCR register value stored into the channel could already have its EN bit set. This would lead to a bad transfer since, at start transfer time, enabling the channel while other registers aren't yet properly set. To avoid this, ensure to mask the CCR_EN bit when storing the ccr value into the mdma channel structure. Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: stable@vger.kernel.org --- drivers/dma/stm32-mdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Comments
Hi Amélie, thanks a lot. Tested-by: Alain Volmat <alain.volmat@foss.st.com> Regards, Alain On Mon, Oct 09, 2023 at 10:24:50AM +0200, Amelie Delaunay wrote: > From: Alain Volmat <alain.volmat@foss.st.com> > > In case of the prep descriptor while the channel is already running, the > CCR register value stored into the channel could already have its EN bit > set. This would lead to a bad transfer since, at start transfer time, > enabling the channel while other registers aren't yet properly set. > To avoid this, ensure to mask the CCR_EN bit when storing the ccr value > into the mdma channel structure. > > Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") > Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > Cc: stable@vger.kernel.org > --- > drivers/dma/stm32-mdma.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c > index bae08b3f55c7..f414efdbd809 100644 > --- a/drivers/dma/stm32-mdma.c > +++ b/drivers/dma/stm32-mdma.c > @@ -489,7 +489,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, > src_maxburst = chan->dma_config.src_maxburst; > dst_maxburst = chan->dma_config.dst_maxburst; > > - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); > + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; > ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); > ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); > > @@ -965,7 +965,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, > if (!desc) > return NULL; > > - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); > + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; > ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); > ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); > cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)); > -- > 2.25.1 >
On 09-10-23, 11:02, Alain Volmat wrote: > Hi Amélie, > > thanks a lot. > > Tested-by: Alain Volmat <alain.volmat@foss.st.com> Please **do ** not ** top post! > > Regards, > Alain > > On Mon, Oct 09, 2023 at 10:24:50AM +0200, Amelie Delaunay wrote: > > From: Alain Volmat <alain.volmat@foss.st.com> > > > > In case of the prep descriptor while the channel is already running, the > > CCR register value stored into the channel could already have its EN bit > > set. This would lead to a bad transfer since, at start transfer time, > > enabling the channel while other registers aren't yet properly set. > > To avoid this, ensure to mask the CCR_EN bit when storing the ccr value > > into the mdma channel structure. > > > > Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") > > Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > > Cc: stable@vger.kernel.org > > --- > > drivers/dma/stm32-mdma.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c > > index bae08b3f55c7..f414efdbd809 100644 > > --- a/drivers/dma/stm32-mdma.c > > +++ b/drivers/dma/stm32-mdma.c > > @@ -489,7 +489,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, > > src_maxburst = chan->dma_config.src_maxburst; > > dst_maxburst = chan->dma_config.dst_maxburst; > > > > - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); > > + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; > > ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); > > ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); > > > > @@ -965,7 +965,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, > > if (!desc) > > return NULL; > > > > - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); > > + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; > > ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); > > ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); > > cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)); > > -- > > 2.25.1 > >
On Mon, 09 Oct 2023 10:24:50 +0200, Amelie Delaunay wrote: > In case of the prep descriptor while the channel is already running, the > CCR register value stored into the channel could already have its EN bit > set. This would lead to a bad transfer since, at start transfer time, > enabling the channel while other registers aren't yet properly set. > To avoid this, ensure to mask the CCR_EN bit when storing the ccr value > into the mdma channel structure. > > [...] Applied, thanks! [1/1] dmaengine: stm32-mdma: correct desc prep when channel running commit: 03f25d53b145bc2f7ccc82fc04e4482ed734f524 Best regards,
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c index bae08b3f55c7..f414efdbd809 100644 --- a/drivers/dma/stm32-mdma.c +++ b/drivers/dma/stm32-mdma.c @@ -489,7 +489,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, src_maxburst = chan->dma_config.src_maxburst; dst_maxburst = chan->dma_config.dst_maxburst; - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); @@ -965,7 +965,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, if (!desc) return NULL; - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));