Message ID | 20221014102029.1162-1-allen-kh.cheng@mediatek.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l1-20020a635701000000b00438d11be245si2180632pgb.429.2022.10.14.03.36.50; Fri, 14 Oct 2022 03:37:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=crvxpsJo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbiJNKWO (ORCPT <rfc822;ouuuleilei@gmail.com> + 99 others); Fri, 14 Oct 2022 06:22:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229633AbiJNKWM (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 14 Oct 2022 06:22:12 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A66C1B867E; Fri, 14 Oct 2022 03:22:06 -0700 (PDT) X-UUID: 1c96c13c1224425bb2747da53a5f5f47-20221014 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=1EVtCMCEdutuhUNCrNtPVBANOTU4/N44AAt3ryFs7N0=; b=crvxpsJocBUOzCEOqnQJSd01HAN9UMcKjOQri5P39mQxzI2wIqCnZE2P0noLDNGPZFsIT3hLrSJeefFnTGNtesT7NZGIG4pGRC92rpwR4f6G48gW+3Cn4tCQ4GbtkPxT6tNGyFKDFixWxBipsSChwDfP/L7R2GevDhehc9TXudY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:bf3a6cab-0045-4e2b-91cd-101521b671be,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:965d17b6-a023-44ff-92b1-76c504f71c7a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 1c96c13c1224425bb2747da53a5f5f47-20221014 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from <allen-kh.cheng@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2005646948; Fri, 14 Oct 2022 18:22:00 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 14 Oct 2022 18:21:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 14 Oct 2022 18:21:59 +0800 From: Allen-KH Cheng <allen-kh.cheng@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com> CC: <angelogioacchino.delregno@collabora.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, Chun-Jie Chen <chun-jie.chen@mediatek.com>, Allen-KH Cheng <allen-kh.cheng@mediatek.com> Subject: [PATCH] soc: mediatek: pm-domains: Fix the power glitch issue Date: Fri, 14 Oct 2022 18:20:29 +0800 Message-ID: <20221014102029.1162-1-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746659004346761581?= X-GMAIL-MSGID: =?utf-8?q?1746659004346761581?= |
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soc: mediatek: pm-domains: Fix the power glitch issue
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Commit Message
Allen-KH Cheng
Oct. 14, 2022, 10:20 a.m. UTC
From: Chun-Jie Chen <chun-jie.chen@mediatek.com> Power reset maybe generate unexpected signal. In order to avoid the glitch issue, we need to enable isolation first to guarantee the stable signal when power reset is triggered. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> --- Resend a PATCH from https://patchwork.kernel.org/project/linux-mediatek/patch/20220310011548.2487-1-chun-jie.chen@mediatek.com/ [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] --- --- drivers/soc/mediatek/mtk-pm-domains.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Comments
Il 14/10/22 12:20, Allen-KH Cheng ha scritto: > From: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > Power reset maybe generate unexpected signal. In order to avoid > the glitch issue, we need to enable isolation first to guarantee the > stable signal when power reset is triggered. > > Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Hey maintainer, Gentle ping for this one. Cheers, Allen On Fri, 2022-10-14 at 12:30 +0200, AngeloGioacchino Del Regno wrote: > Il 14/10/22 12:20, Allen-KH Cheng ha scritto: > > From: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > > > Power reset maybe generate unexpected signal. In order to avoid > > the glitch issue, we need to enable isolation first to guarantee > > the > > stable signal when power reset is triggered. > > > > Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power > > domains") > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > > Reviewed-by: Miles Chen <miles.chen@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > >
On 14/10/2022 12:20, Allen-KH Cheng wrote: > From: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > Power reset maybe generate unexpected signal. In order to avoid > the glitch issue, we need to enable isolation first to guarantee the > stable signal when power reset is triggered. > > Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > Reviewed-by: Miles Chen <miles.chen@mediatek.com> Applied to fixes now, thanks! > --- > Resend a PATCH from > https://patchwork.kernel.org/project/linux-mediatek/patch/20220310011548.2487-1-chun-jie.chen@mediatek.com/ > > [Allen-KH Cheng <allen-kh.cheng@mediatek.com>] > --- > --- > drivers/soc/mediatek/mtk-pm-domains.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c > index 09e3c38b8466..474b272f9b02 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.c > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > @@ -275,9 +275,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); > > /* subsys power off */ > - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); > regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); > + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); >
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 09e3c38b8466..474b272f9b02 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -275,9 +275,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); /* subsys power off */ - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);