diff mbox series

[v3,3/3] perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models

Message ID 20221109082802.27543-4-likexu@tencent.com
State New
Headers
Series KVM: x86/pmu: Enable guest PEBS for SPR and later models |

Commit Message

Like Xu Nov. 9, 2022, 8:28 a.m. UTC 
  From: Like Xu <likexu@tencent.com>

According to Intel SDM, the EPT-friendly PEBS is supported by all the
platforms after ICX, ADL and the future platforms with PEBS format 5.

Currently the only in-kernel user of this capability is KVM, which has
very limited support for hybrid core pmu, so ADL and its successors do
not currently expose this capability. When both hybrid core and PEBS
format 5 are present, KVM will decide on its own merits.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-perf-users@vger.kernel.org
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
---
Nit: This change is proposed to be applied via the KVM tree.

 arch/x86/events/intel/core.c | 1 +
 arch/x86/events/intel/ds.c   | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

Comments

Peter Zijlstra Nov. 14, 2022, 12:46 p.m. UTC | #1 
On Wed, Nov 09, 2022 at 04:28:02PM +0800, Like Xu wrote:
> From: Like Xu <likexu@tencent.com>
> 
> According to Intel SDM, the EPT-friendly PEBS is supported by all the
> platforms after ICX, ADL and the future platforms with PEBS format 5.
> 
> Currently the only in-kernel user of this capability is KVM, which has
> very limited support for hybrid core pmu, so ADL and its successors do
> not currently expose this capability. When both hybrid core and PEBS
> format 5 are present, KVM will decide on its own merits.

Oh right; the whole ADL KVM trainwreck :/ What's the plan there?

> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: linux-perf-users@vger.kernel.org
> Suggested-by: Kan Liang <kan.liang@linux.intel.com>
> Signed-off-by: Like Xu <likexu@tencent.com>
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
> ---
> Nit: This change is proposed to be applied via the KVM tree.

Works for me;

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Like Xu Nov. 15, 2022, 7:16 a.m. UTC | #2 
On 14/11/2022 8:46 pm, Peter Zijlstra wrote:
> On Wed, Nov 09, 2022 at 04:28:02PM +0800, Like Xu wrote:
>> From: Like Xu <likexu@tencent.com>
>>
>> According to Intel SDM, the EPT-friendly PEBS is supported by all the
>> platforms after ICX, ADL and the future platforms with PEBS format 5.
>>
>> Currently the only in-kernel user of this capability is KVM, which has
>> very limited support for hybrid core pmu, so ADL and its successors do
>> not currently expose this capability. When both hybrid core and PEBS
>> format 5 are present, KVM will decide on its own merits.
> 
> Oh right; the whole ADL KVM trainwreck :/ What's the plan there?

As we know, our community doesn't really have a plan in terms of feature reception,
considering hyprid pmu doesn't have market share in the data center (where most KVM
users are, and the test farms), and KVM-based client hypervisor will actively 
control the
cpu that the KVM module initializes, and adds more trainwreck, so as of now I don't
have a timeline for vPMU on ADL+ (until there are noteworthy user complaints).

Please let me know if you and Kan have other input.

> 
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: linux-perf-users@vger.kernel.org
>> Suggested-by: Kan Liang <kan.liang@linux.intel.com>
>> Signed-off-by: Like Xu <likexu@tencent.com>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>> ---
>> Nit: This change is proposed to be applied via the KVM tree.
> 
> Works for me;
> 
> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
diff mbox series

Patch

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a646a5f9a235..15e061fbb2f3 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6350,6 +6350,7 @@  __init int intel_pmu_init(void)
 		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
 		x86_pmu.extra_regs = intel_spr_extra_regs;
 		x86_pmu.limit_period = spr_limit_period;
+		x86_pmu.pebs_ept = 1;
 		x86_pmu.pebs_aliases = NULL;
 		x86_pmu.pebs_prec_dist = true;
 		x86_pmu.pebs_block = true;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 7839507b3844..185e66b4ce31 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2293,8 +2293,10 @@  void __init intel_ds_init(void)
 			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
 			break;
 
-		case 4:
 		case 5:
+			x86_pmu.pebs_ept = 1;
+			fallthrough;
+		case 4:
 			x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
 			x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
 			if (x86_pmu.intel_cap.pebs_baseline) {