diff mbox series

[v2] RISC-V: const: hide mvconst splitter from IRA

Message ID 20231006174954.392381-1-vineetg@rivosinc.com
State Accepted
Headers
Series [v2] RISC-V: const: hide mvconst splitter from IRA |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Vineet Gupta Oct. 6, 2023, 5:49 p.m. UTC 
  Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.

Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code for constants (and sometimes no code at all).

See PR/109279 (large constant), PR/110748 (const -0.0) ...

Granted the IRA logic is subsided with -fsched-pressure which is now
enabled for RISC-V backend, the gate makes this future-proof in
addition to helping with -O1 etc.

This fixes 1 addition test

               ========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ | gfortran |

   rv32imac/  ilp32/ medlow |  416 /   103 |   13 /     6 |   67 /    12 |
 rv32imafdc/ ilp32d/ medlow |  416 /   103 |   13 /     6 |   24 /     4 |
   rv64imac/   lp64/ medlow |  417 /   104 |    9 /     3 |   67 /    12 |
 rv64imafdc/  lp64d/ medlow |  416 /   103 |    5 /     2 |    6 /     1 |

Also similar to v1, this doesn't move RISC-V SPEC scores at all.

gcc/ChangeLog:
	* config/riscv/riscv.md (mvconst_internal): Add !ira_in_progress.

Suggested-by: Jeff Law <jeffreyalaw@gmail.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
changes since v1:
  - Fix bug: new condition to prevent recognition not splitting itself
---
 gcc/config/riscv/riscv.md | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Jeff Law Oct. 6, 2023, 5:59 p.m. UTC | #1 
On 10/6/23 11:49, Vineet Gupta wrote:
> Vlad recently introduced a new gate @ira_in_progress, similar to
> counterparts @{reload,lra}_in_progress.
> 
> Use this to hide the constant synthesis splitter from being recog* ()
> by IRA register equivalence logic which is eager to undo the splits,
> generating worse code for constants (and sometimes no code at all).
> 
> See PR/109279 (large constant), PR/110748 (const -0.0) ...
> 
> Granted the IRA logic is subsided with -fsched-pressure which is now
> enabled for RISC-V backend, the gate makes this future-proof in
> addition to helping with -O1 etc.
> 
> This fixes 1 addition test
> 
>                 ========= Summary of gcc testsuite =========
>                              | # of unexpected case / # of unique unexpected case
>                              |          gcc |          g++ | gfortran |
> 
>     rv32imac/  ilp32/ medlow |  416 /   103 |   13 /     6 |   67 /    12 |
>   rv32imafdc/ ilp32d/ medlow |  416 /   103 |   13 /     6 |   24 /     4 |
>     rv64imac/   lp64/ medlow |  417 /   104 |    9 /     3 |   67 /    12 |
>   rv64imafdc/  lp64d/ medlow |  416 /   103 |    5 /     2 |    6 /     1 |
> 
> Also similar to v1, this doesn't move RISC-V SPEC scores at all.
> 
> gcc/ChangeLog:
> 	* config/riscv/riscv.md (mvconst_internal): Add !ira_in_progress.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e00b8ee3579d..9b990ec2566d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1997,13 +1997,16 @@ 
 
 ;; Pretend to have the ability to load complex const_int in order to get
 ;; better code generation around them.
-;;
 ;; But avoid constants that are special cased elsewhere.
+;;
+;; Hide it from IRA register equiv recog* () to elide potential undoing of split
+;;
 (define_insn_and_split "*mvconst_internal"
   [(set (match_operand:GPR 0 "register_operand" "=r")
         (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
-  "!(p2m1_shift_operand (operands[1], <MODE>mode)
-     || high_mask_shift_operand (operands[1], <MODE>mode))"
+  "!ira_in_progress
+   && !(p2m1_shift_operand (operands[1], <MODE>mode)
+        || high_mask_shift_operand (operands[1], <MODE>mode))"
   "#"
   "&& 1"
   [(const_int 0)]