diff mbox series

[2/2] clk: qcom: gcc-sc8280xp: Don't keep display AHB clocks always-on

Message ID 20230929-topic-8280_ahbdisp-v1-2-72bdc38309b9@linaro.org
State New
Headers
Series 8280 display ahb clk fixes |

Commit Message

Konrad Dybcio Sept. 29, 2023, 1:38 p.m. UTC 
  These clocks are consumed by the dispcc[01] clock controllers, so there's
no reason to keep them on from gcc probe. Remove that hack.

Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/clk/qcom/gcc-sc8280xp.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

Comments

Johan Hovold Sept. 30, 2023, 9:39 a.m. UTC | #1 
On Fri, Sep 29, 2023 at 03:38:53PM +0200, Konrad Dybcio wrote:
> These clocks are consumed by the dispcc[01] clock controllers, so there's
> no reason to keep them on from gcc probe. Remove that hack.

Eh, how did you test this patch?

The GCC_DISP_AHB_CLK clocks are not modelled by the clock driver
currently so nothing is guaranteeing them to be enabled if we were to
apply this patch. They just happen to be left on by the bootloader on
some machines currently (well at least one of them is on one machine).

So this series is broken and should not be applied.

NAK.

Also, please CC me on sc8280xp and X13s related patches.
 
> Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/clk/qcom/gcc-sc8280xp.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
> index bfb77931e868..bf95f82a3818 100644
> --- a/drivers/clk/qcom/gcc-sc8280xp.c
> +++ b/drivers/clk/qcom/gcc-sc8280xp.c
> @@ -7545,18 +7545,16 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
>  
>  	/*
>  	 * Keep the clocks always-ON
> -	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK,
> +	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK,
>  	 * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK,
> -	 * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK
> +	 * GCC_VIDEO_XO_CLK, GCC_DISP1_XO_CLK
>  	 */
>  	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
>  	regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0));
> -	regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
>  	regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0));
>  	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
>  	regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
>  	regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0));
> -	regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0));
>  	regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0));

Johan
Konrad Dybcio Sept. 30, 2023, 4:44 p.m. UTC | #2 
On 9/30/23 11:39, Johan Hovold wrote:
> On Fri, Sep 29, 2023 at 03:38:53PM +0200, Konrad Dybcio wrote:
>> These clocks are consumed by the dispcc[01] clock controllers, so there's
>> no reason to keep them on from gcc probe. Remove that hack.
> 
> Eh, how did you test this patch?
Oehh you're right, I didn't notice that I still had clk_ignore_unused :/

> 
> The GCC_DISP_AHB_CLK clocks are not modelled by the clock driver
> currently so nothing is guaranteeing them to be enabled if we were to
> apply this patch. They just happen to be left on by the bootloader on
> some machines currently (well at least one of them is on one machine).
What fooled me is that despite not being modeled by the clock driver, it 
is defined in bindings and referenced in the device tree.

Another thing I'll fix up!

> So this series is broken and should not be applied.
Agreed, I'll revisit this tonight or next week.

> 
> NAK.
> 
> Also, please CC me on sc8280xp and X13s related patches.
Omitting you was not intentional, sorry!

Konrad
Johan Hovold Oct. 2, 2023, 8:34 a.m. UTC | #3 
On Sat, Sep 30, 2023 at 06:44:47PM +0200, Konrad Dybcio wrote:
> On 9/30/23 11:39, Johan Hovold wrote:
> > On Fri, Sep 29, 2023 at 03:38:53PM +0200, Konrad Dybcio wrote:
> >> These clocks are consumed by the dispcc[01] clock controllers, so there's
> >> no reason to keep them on from gcc probe. Remove that hack.
> > 
> > Eh, how did you test this patch?

> Oehh you're right, I didn't notice that I still had clk_ignore_unused :/

That doesn't matter since these clocks are never even registered with
the clock framework.

But you'd notice that if you try to verify the clock state by looking at
/sys/kernel/debug/clk/clk_summary for example.

> > The GCC_DISP_AHB_CLK clocks are not modelled by the clock driver
> > currently so nothing is guaranteeing them to be enabled if we were to
> > apply this patch. They just happen to be left on by the bootloader on
> > some machines currently (well at least one of them is on one machine).

> What fooled me is that despite not being modeled by the clock driver, it 
> is defined in bindings and referenced in the device tree.
> 
> Another thing I'll fix up!

Right, a number of Qualcomm SoCs apparently fail to register these
clocks. You should start by determining why that is as I assume (hope)
it was done for a reason.

Then the Qualcomm drivers use sloppy bulk clock look-up and enable so
that an integrator would never even notice when clocks are missing. Once
the clocks are registered, that could be tightened up as well.

Johan
Konrad Dybcio Oct. 2, 2023, 9:13 a.m. UTC | #4 
On 10/2/23 10:34, Johan Hovold wrote:
> On Sat, Sep 30, 2023 at 06:44:47PM +0200, Konrad Dybcio wrote:
>> On 9/30/23 11:39, Johan Hovold wrote:
>>> On Fri, Sep 29, 2023 at 03:38:53PM +0200, Konrad Dybcio wrote:
>>>> These clocks are consumed by the dispcc[01] clock controllers, so there's
>>>> no reason to keep them on from gcc probe. Remove that hack.
>>>
>>> Eh, how did you test this patch?
> 
>> Oehh you're right, I didn't notice that I still had clk_ignore_unused :/
> 
> That doesn't matter since these clocks are never even registered with
> the clock framework.
That's the point, if it was missing and was not enabled I would have 
noticed display not working (unless the bootloader left it on, which it 
did for at least the mdss instance with the eDP panel)

> 
> But you'd notice that if you try to verify the clock state by looking at
> /sys/kernel/debug/clk/clk_summary for example.
> 
>>> The GCC_DISP_AHB_CLK clocks are not modelled by the clock driver
>>> currently so nothing is guaranteeing them to be enabled if we were to
>>> apply this patch. They just happen to be left on by the bootloader on
>>> some machines currently (well at least one of them is on one machine).
> 
>> What fooled me is that despite not being modeled by the clock driver, it
>> is defined in bindings and referenced in the device tree.
>>
>> Another thing I'll fix up!
> 
> Right, a number of Qualcomm SoCs apparently fail to register these
> clocks. You should start by determining why that is as I assume (hope)
> it was done for a reason.
The reason is, downstream lazily enables clocks because people decided 
they don't leak much power and are still enabled after a clock 
controller reset (or something) and we started blindly copying that 
around 2017 :/

> 
> Then the Qualcomm drivers use sloppy bulk clock look-up and enable so
> that an integrator would never even notice when clocks are missing. Once
> the clocks are registered, that could be tightened up as well.
Yeah the current state of things is not great.

Konrad
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index bfb77931e868..bf95f82a3818 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -7545,18 +7545,16 @@  static int gcc_sc8280xp_probe(struct platform_device *pdev)
 
 	/*
 	 * Keep the clocks always-ON
-	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK,
+	 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK,
 	 * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK,
-	 * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK
+	 * GCC_VIDEO_XO_CLK, GCC_DISP1_XO_CLK
 	 */
 	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
 	regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0));
-	regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
 	regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0));
 	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
 	regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
 	regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0));
-	regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0));
 	regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0));
 
 	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));