[v3,01/12] dt-bindings: net: add STM32MP13 compatible in documentation for stm32
Commit Message
New STM32 SOC have 2 GMACs instances.
GMAC IP version is SNPS 4.20.
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
---
.../devicetree/bindings/net/stm32-dwmac.yaml | 78 +++++++++++++++++--
1 file changed, 70 insertions(+), 8 deletions(-)
Comments
Hey,
On Thu, Sep 28, 2023 at 05:15:01PM +0200, Christophe Roullier wrote:
> New STM32 SOC have 2 GMACs instances.
> GMAC IP version is SNPS 4.20.
>
> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
> ---
> .../devicetree/bindings/net/stm32-dwmac.yaml | 78 +++++++++++++++++--
> 1 file changed, 70 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> index fc8c96b08d7dc..ca976281bfc22 100644
> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
> @@ -22,18 +22,17 @@ select:
> enum:
> - st,stm32-dwmac
> - st,stm32mp1-dwmac
> + - st,stm32mp13-dwmac
> required:
> - compatible
>
> -allOf:
> - - $ref: snps,dwmac.yaml#
> -
> properties:
> compatible:
> oneOf:
> - items:
> - enum:
> - st,stm32mp1-dwmac
> + - st,stm32mp13-dwmac
> - const: snps,dwmac-4.20a
> - items:
> - enum:
> @@ -74,13 +73,10 @@ properties:
>
> st,syscon:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> - items:
> - - items:
> - - description: phandle to the syscon node which encompases the glue register
> - - description: offset of the control register
> description:
> Should be phandle/offset pair. The phandle to the syscon node which
> - encompases the glue register, and the offset of the control register
> + encompases the glue register, the offset of the control register and
> + the mask to set bitfield in control register
>
> st,eth-clk-sel:
> description:
> @@ -101,6 +97,38 @@ required:
>
> unevaluatedProperties: false
>
> +allOf:
> + - $ref: snps,dwmac.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - st,stm32mp1-dwmac
> + - st,stm32-dwmac
> + then:
> + properties:
> + st,syscon:
> + items:
> + items:
> + - description: phandle to the syscon node which encompases the glue register
> + - description: offset of the control register
These descriptions should, IMO, be moved back out to the st,syscon
definition. If you put the 3 descriptions there, with "minItems: 2" &
put "maxItems: 2" and "minItems: 3" in each of the if/then clauses.
Also, it should be sufficient to simplify to if/then/else.
Cheers,
Conor.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - st,stm32mp13-dwmac
> + then:
> + properties:
> + st,syscon:
> + items:
> + items:
> + - description: phandle to the syscon node which encompases the glue register
> + - description: offset of the control register
> + - description: field to set mask in register
> +
> examples:
> - |
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -161,3 +189,37 @@ examples:
> snps,pbl = <8>;
> phy-mode = "mii";
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/stm32mp1-clks.h>
> + #include <dt-bindings/reset/stm32mp1-resets.h>
> + #include <dt-bindings/mfd/stm32h7-rcc.h>
> + //Example 4
> + ethernet3: ethernet@5800a000 {
> + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
> + reg = <0x5800a000 0x2000>;
> + reg-names = "stmmaceth";
> + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <&exti 68 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "eth_wake_irq";
> + clock-names = "stmmaceth",
> + "mac-clk-tx",
> + "mac-clk-rx",
> + "eth-ck",
> + "ptp_ref",
> + "ethstp";
> + clocks = <&rcc ETHMAC>,
> + <&rcc ETHTX>,
> + <&rcc ETHRX>,
> + <&rcc ETHCK_K>,
> + <&rcc ETHPTP_K>,
> + <&rcc ETHSTP>;
> + st,syscon = <&syscfg 0x4 0xff0000>;
> + snps,mixed-burst;
> + snps,pbl = <2>;
> + snps,axi-config = <&stmmac_axi_config_1>;
> + snps,tso;
> + phy-mode = "rmii";
> + };
> --
> 2.25.1
>
On 28/09/2023 22:39, Conor Dooley wrote:
> Hey,
>
> On Thu, Sep 28, 2023 at 05:15:01PM +0200, Christophe Roullier wrote:
>> New STM32 SOC have 2 GMACs instances.
>> GMAC IP version is SNPS 4.20.
>>
>> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
>> ---
>> .../devicetree/bindings/net/stm32-dwmac.yaml | 78 +++++++++++++++++--
>> 1 file changed, 70 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> index fc8c96b08d7dc..ca976281bfc22 100644
>> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
>> @@ -22,18 +22,17 @@ select:
>> enum:
>> - st,stm32-dwmac
>> - st,stm32mp1-dwmac
>> + - st,stm32mp13-dwmac
>> required:
>> - compatible
>>
>> -allOf:
>> - - $ref: snps,dwmac.yaml#
>> -
>> properties:
>> compatible:
>> oneOf:
>> - items:
>> - enum:
>> - st,stm32mp1-dwmac
>> + - st,stm32mp13-dwmac
>> - const: snps,dwmac-4.20a
>> - items:
>> - enum:
>> @@ -74,13 +73,10 @@ properties:
>>
>> st,syscon:
>> $ref: /schemas/types.yaml#/definitions/phandle-array
>> - items:
>> - - items:
>> - - description: phandle to the syscon node which encompases the glue register
>> - - description: offset of the control register
>> description:
>> Should be phandle/offset pair. The phandle to the syscon node which
>> - encompases the glue register, and the offset of the control register
>> + encompases the glue register, the offset of the control register and
>> + the mask to set bitfield in control register
>>
>> st,eth-clk-sel:
>> description:
>> @@ -101,6 +97,38 @@ required:
>>
>> unevaluatedProperties: false
>>
>> +allOf:
>> + - $ref: snps,dwmac.yaml#
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - st,stm32mp1-dwmac
>> + - st,stm32-dwmac
>> + then:
>> + properties:
>> + st,syscon:
>> + items:
>> + items:
>> + - description: phandle to the syscon node which encompases the glue register
>> + - description: offset of the control register
>
> These descriptions should, IMO, be moved back out to the st,syscon
> definition. If you put the 3 descriptions there, with "minItems: 2" &
> put "maxItems: 2" and "minItems: 3" in each of the if/then clauses.
> Also, it should be sufficient to simplify to if/then/else.
What's more, same property should not have different types. This syscon
property was way too generic, thus now you have trouble of conflicting
types.
Best regards,
Krzysztof
@@ -22,18 +22,17 @@ select:
enum:
- st,stm32-dwmac
- st,stm32mp1-dwmac
+ - st,stm32mp13-dwmac
required:
- compatible
-allOf:
- - $ref: snps,dwmac.yaml#
-
properties:
compatible:
oneOf:
- items:
- enum:
- st,stm32mp1-dwmac
+ - st,stm32mp13-dwmac
- const: snps,dwmac-4.20a
- items:
- enum:
@@ -74,13 +73,10 @@ properties:
st,syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- - items:
- - description: phandle to the syscon node which encompases the glue register
- - description: offset of the control register
description:
Should be phandle/offset pair. The phandle to the syscon node which
- encompases the glue register, and the offset of the control register
+ encompases the glue register, the offset of the control register and
+ the mask to set bitfield in control register
st,eth-clk-sel:
description:
@@ -101,6 +97,38 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp1-dwmac
+ - st,stm32-dwmac
+ then:
+ properties:
+ st,syscon:
+ items:
+ items:
+ - description: phandle to the syscon node which encompases the glue register
+ - description: offset of the control register
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp13-dwmac
+ then:
+ properties:
+ st,syscon:
+ items:
+ items:
+ - description: phandle to the syscon node which encompases the glue register
+ - description: offset of the control register
+ - description: field to set mask in register
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -161,3 +189,37 @@ examples:
snps,pbl = <8>;
phy-mode = "mii";
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ #include <dt-bindings/mfd/stm32h7-rcc.h>
+ //Example 4
+ ethernet3: ethernet@5800a000 {
+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "eth-ck",
+ "ptp_ref",
+ "ethstp";
+ clocks = <&rcc ETHMAC>,
+ <&rcc ETHTX>,
+ <&rcc ETHRX>,
+ <&rcc ETHCK_K>,
+ <&rcc ETHPTP_K>,
+ <&rcc ETHSTP>;
+ st,syscon = <&syscfg 0x4 0xff0000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_1>;
+ snps,tso;
+ phy-mode = "rmii";
+ };