Message ID | 20230926093121.18676-4-yi.l.liu@intel.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp1973616vqu; Tue, 26 Sep 2023 07:52:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGEfnu6Ka8na4/d8532SyuRxkkfoyuu8jOn4SdarXPzKDqKT3iE071RXKWZvmThG9ozOq4W X-Received: by 2002:aa7:8893:0:b0:690:2ecd:a597 with SMTP id z19-20020aa78893000000b006902ecda597mr10287291pfe.21.1695739943271; Tue, 26 Sep 2023 07:52:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695739943; cv=none; d=google.com; s=arc-20160816; b=YstuYZXf1BgrIbk6qBtM1q3HbPrJb0mW3ruBpIsJKsGWMNsY9D8KKun1Dg+Z16LuNX /razBDRCSotxwUpscV2qnlJZhBnuBD8bhmW5sSIzHvK2qnuE0nol4t6+09x1wNC6VLWU gLJLMIDdB9B8J09UWPyfwekPUhupK8SNg2DZhyK1keMuOJYGgRhCk5VxMCNYSOo1EFcr zAlA3DFXgp0TbQBo22bW8/YoYfmuw+CW9opSQgduTtuKCb7lPp23FsdePz5D/iEqldFn TubBo4yryqQt9fCtrKIsPsxtItqtlmF3vTyrWiX82yGJ3rcJoKMEKLFjNiBMy1zUHfUb 8PGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=chqNXPWoxq6NAS2n5n8XL0z9LhMbkxnIDip8oI3wTTE=; fh=Kv+cxc+457xZThbZHBdHDWxamNAAkIiByoci0wEvMsM=; b=hde++UX2vfndsxFpQr++hy+AALY9jBqjwAIHloXB+mFR5cCACWvPeJfp/HwdTKD9+V /2VPI/Ocps/cMdK4tA7FwzVjXqov0f8DELUj6NrqTHHHdLipJfhm0dtaeIGxcRyAcY9t 3X8S+tHt1F5fPsfpp9LIrgGyeYAsjQHZSf2kADADw9CS+lNr0S7J7zwpWm/0AfgVmv/C 6d0lGwFkvgDI4CmzPbRfakaUQCJOVnL0l50GqKTlSoeAVPqh0KvYUKYz6M7M77zKx2LG faENquc0SXaHee4zCzODC1lGOEB9S8LTsDYJWKNFzTVicYfO7ZRrhZNC8N215oJyf6yj 4Qqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CsFHfwDj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id a21-20020a63e855000000b00578d7a3a4fdsi12679850pgk.563.2023.09.26.07.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 07:52:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CsFHfwDj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id D26E0801B67D; Tue, 26 Sep 2023 02:36:12 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233940AbjIZJfg (ORCPT <rfc822;ruipengqi7@gmail.com> + 27 others); Tue, 26 Sep 2023 05:35:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234114AbjIZJfT (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 26 Sep 2023 05:35:19 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 035FEF3; Tue, 26 Sep 2023 02:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695720913; x=1727256913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bZj72hwk6aGVHqUfVsQNiXvoc1GB8ZJ+RY64a2dEVnk=; b=CsFHfwDjUPio3TMeQ2KS9igb5wWbW/08xnYhqcUybO0NggZHh19kwHyS zfDr9YI0ht/JkwU0sUIZkmzL/dz3nLYJkZ4wIc47evQ6z8tA2v1zhUc5t uOfB7Khf9qO5+w0fGR4A/6N+HDM9qkxrjpvJ+1M80GXqZVEZQ4QSNxm+m 30lC/HqCC9+K8kv6MZcJw/TNjs5E2YmweYPrjJQzuzW9y6o4fCzJfPmKz A6T2NGk1UwqBmYDlKdv2LIv1flPwHNfxsHTAMqY9KdR9CIbwb7ELoTalM Bp2FZgH+OggPdYuwpW4kUhQgVMGPOg50lLIjgbwIq+xeadLWGUVZcNihI A==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="412442921" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="412442921" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 02:31:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="725373049" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="725373049" Received: from 984fee00a4c6.jf.intel.com ([10.165.58.231]) by orsmga006.jf.intel.com with ESMTP; 26 Sep 2023 02:31:26 -0700 From: Yi Liu <yi.l.liu@intel.com> To: alex.williamson@redhat.com, jgg@nvidia.com, kevin.tian@intel.com, robin.murphy@arm.com, baolu.lu@linux.intel.com Cc: joro@8bytes.org, cohuck@redhat.com, eric.auger@redhat.com, nicolinc@nvidia.com, kvm@vger.kernel.org, mjrosato@linux.ibm.com, chao.p.peng@linux.intel.com, yi.l.liu@intel.com, yi.y.sun@linux.intel.com, peterx@redhat.com, jasowang@redhat.com, shameerali.kolothum.thodi@huawei.com, lulu@redhat.com, suravee.suthikulpanit@amd.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, zhenzhong.duan@intel.com, joao.m.martins@oracle.com Subject: [RFC 3/3] vfio/pci: Expose PCIe PASID capability to userspace Date: Tue, 26 Sep 2023 02:31:21 -0700 Message-Id: <20230926093121.18676-4-yi.l.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230926093121.18676-1-yi.l.liu@intel.com> References: <20230926093121.18676-1-yi.l.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 26 Sep 2023 02:36:12 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778112206673291284 X-GMAIL-MSGID: 1778112206673291284 |
Series |
vfio-pci support pasid attach/detach
|
|
Commit Message
Yi Liu
Sept. 26, 2023, 9:31 a.m. UTC
This exposes PCIe PASID capability to userspace and where to emulate this
capability if wants to further expose it to VM.
And this only exposes PASID capability for devices which has PCIe PASID
extended struture in its configuration space. While for VFs, userspace
is still unable to see this capability as SR-IOV spec forbides VF to
implement PASID capability extended structure. It is a TODO in future.
Related discussion can be found in below links:
https://lore.kernel.org/kvm/20200407095801.648b1371@w520.home/
https://lore.kernel.org/kvm/BL1PR11MB5271A60035EF591A5BE8AC878C01A@BL1PR11MB5271.namprd11.prod.outlook.com/
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
---
drivers/vfio/pci/vfio_pci_config.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
> From: Liu, Yi L <yi.l.liu@intel.com> > Sent: Tuesday, September 26, 2023 5:31 PM > > This exposes PCIe PASID capability to userspace and where to emulate this > capability if wants to further expose it to VM. > > And this only exposes PASID capability for devices which has PCIe PASID > extended struture in its configuration space. While for VFs, userspace > is still unable to see this capability as SR-IOV spec forbides VF to > implement PASID capability extended structure. It is a TODO in future. > Related discussion can be found in below links: > > https://lore.kernel.org/kvm/20200407095801.648b1371@w520.home/ > https://lore.kernel.org/kvm/BL1PR11MB5271A60035EF591A5BE8AC878C01A > @BL1PR11MB5271.namprd11.prod.outlook.com/ > Yes, we need a decision for VF case. If the consensus is to continue exposing the PASID capability in vfio-pci config space by developing a kernel quirk mechanism to find offset for VF, then this patch for PF is orthogonal to that VF work and can go as it is. But if the decision is to have a device feature for the user to enumerate the vPASID capability and let the VMM take care of finding the vPASID cap offset, then better we start doing that for PF too since it's not good to have two enumeration interfaces for PF/VF respectively. My preference is via device feature given Qemu already includes lots of quirks for vfio-pci devices. Another reason is that when supporting vPASID with SIOV there are some arch constraints which the driver needs to report to the user to follow (e.g. don't assign ENQCMD-capable sibling vdev's to a same guest, etc.). A device feature interface can better encapsulate everything related to vPASID in one place. Thanks Kevin
On Wed, 27 Sep 2023 08:07:54 +0000 "Tian, Kevin" <kevin.tian@intel.com> wrote: > > From: Liu, Yi L <yi.l.liu@intel.com> > > Sent: Tuesday, September 26, 2023 5:31 PM > > > > This exposes PCIe PASID capability to userspace and where to emulate this > > capability if wants to further expose it to VM. > > > > And this only exposes PASID capability for devices which has PCIe PASID > > extended struture in its configuration space. While for VFs, userspace > > is still unable to see this capability as SR-IOV spec forbides VF to > > implement PASID capability extended structure. It is a TODO in future. > > Related discussion can be found in below links: > > > > https://lore.kernel.org/kvm/20200407095801.648b1371@w520.home/ > > https://lore.kernel.org/kvm/BL1PR11MB5271A60035EF591A5BE8AC878C01A > > @BL1PR11MB5271.namprd11.prod.outlook.com/ > > > > Yes, we need a decision for VF case. > > If the consensus is to continue exposing the PASID capability in vfio-pci > config space by developing a kernel quirk mechanism to find offset for > VF, then this patch for PF is orthogonal to that VF work and can go as it is. > > But if the decision is to have a device feature for the user to enumerate > the vPASID capability and let the VMM take care of finding the vPASID > cap offset, then better we start doing that for PF too since it's not good > to have two enumeration interfaces for PF/VF respectively. Note also that QEMU implements a lazy algorithm for exposing capabilities, the default is to expose them, so we need to consider existing VMs seeing a new read-only PASID capability on an assigned PF. That might support an alternate means to expose the capability. > My preference is via device feature given Qemu already includes lots of > quirks for vfio-pci devices. Another reason is that when supporting vPASID > with SIOV there are some arch constraints which the driver needs to > report to the user to follow (e.g. don't assign ENQCMD-capable sibling > vdev's to a same guest, etc.). ?! > A device feature interface can better > encapsulate everything related to vPASID in one place. Sorry if I don't remember, have you posted a proposal for the device feature interface? Thanks, Alex
> From: Alex Williamson <alex.williamson@redhat.com> > Sent: Thursday, September 28, 2023 2:53 AM > > On Wed, 27 Sep 2023 08:07:54 +0000 > "Tian, Kevin" <kevin.tian@intel.com> wrote: > > > > From: Liu, Yi L <yi.l.liu@intel.com> > > > Sent: Tuesday, September 26, 2023 5:31 PM > > > > > > This exposes PCIe PASID capability to userspace and where to emulate > this > > > capability if wants to further expose it to VM. > > > > > > And this only exposes PASID capability for devices which has PCIe PASID > > > extended struture in its configuration space. While for VFs, userspace > > > is still unable to see this capability as SR-IOV spec forbides VF to > > > implement PASID capability extended structure. It is a TODO in future. > > > Related discussion can be found in below links: > > > > > > https://lore.kernel.org/kvm/20200407095801.648b1371@w520.home/ > > > > https://lore.kernel.org/kvm/BL1PR11MB5271A60035EF591A5BE8AC878C01A > > > @BL1PR11MB5271.namprd11.prod.outlook.com/ > > > > > > > Yes, we need a decision for VF case. > > > > If the consensus is to continue exposing the PASID capability in vfio-pci > > config space by developing a kernel quirk mechanism to find offset for > > VF, then this patch for PF is orthogonal to that VF work and can go as it is. > > > > But if the decision is to have a device feature for the user to enumerate > > the vPASID capability and let the VMM take care of finding the vPASID > > cap offset, then better we start doing that for PF too since it's not good > > to have two enumeration interfaces for PF/VF respectively. > > Note also that QEMU implements a lazy algorithm for exposing > capabilities, the default is to expose them, so we need to consider > existing VMs seeing a new read-only PASID capability on an assigned PF. > > That might support an alternate means to expose the capability. Yep. that's also a valid point. > > > My preference is via device feature given Qemu already includes lots of > > quirks for vfio-pci devices. Another reason is that when supporting vPASID > > with SIOV there are some arch constraints which the driver needs to > > report to the user to follow (e.g. don't assign ENQCMD-capable sibling > > vdev's to a same guest, etc.). > > ?! Sorry that I didn't plan to elaborate that tricky constraint before we show the overall SIOV/vPASID implementation. Explaining it requires lots of context and here just want to mention the potential requirement in case we need more proofs to go this direction. 😊 > > > A device feature interface can better > > encapsulate everything related to vPASID in one place. > > Sorry if I don't remember, have you posted a proposal for the device > feature interface? Thanks, > Not yet. Will do in next version.
diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index 7e2e62ab0869..dfae5ad5ebc0 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -95,7 +95,7 @@ static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = { [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ - [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ + [PCI_EXT_CAP_ID_PASID] = PCI_EXT_CAP_PASID_SIZEOF, [PCI_EXT_CAP_ID_DVSEC] = 0xFF, };