diff mbox series

[3/3] drm/msm/dpu: Fix SC7280 DSC block length

Message ID 20230921-topic-7280_dpu-v1-3-6912a97183d5@linaro.org
State New
Headers
Series SC7280 DPU fixups |

Commit Message

Konrad Dybcio Sept. 20, 2023, 10:46 p.m. UTC 
  Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.

Use the correct one this time.

Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Abhinav Kumar Sept. 21, 2023, 12:10 a.m. UTC | #1 
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
> Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
> the block length from a wrong value to another wrong value.
> 
> Use the correct one this time.
> 

No that change is correct as well.

After we moved to sub-blk parsing, we have enc and ctl blocks length 
used from the dsc_sblk_* instead:

static const struct dpu_dsc_sub_blks dsc_sblk_0 = {
         .enc = {.name = "enc", .base = 0x100, .len = 0x9c},
         .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10},
};

static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
         .enc = {.name = "enc", .base = 0x200, .len = 0x9c},
         .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
};

The main block has only one register now which is the DSC_CMN register.

Hence len = 0x4 is correct for that.

Sorry, but this is right too :)

> Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index b6a59d7b94c4..de5e1a57a142 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>   static const struct dpu_dsc_cfg sc7280_dsc[] = {
>   	{
>   		.name = "dce_0_0", .id = DSC_0,
> -		.base = 0x80000, .len = 0x4,
> +		.base = 0x80000, .len = 0x10,
>   		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL),
>   		.sblk = &dsc_sblk_0,
>   	},
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index b6a59d7b94c4..de5e1a57a142 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -163,7 +163,7 @@  static const struct dpu_pingpong_cfg sc7280_pp[] = {
 static const struct dpu_dsc_cfg sc7280_dsc[] = {
 	{
 		.name = "dce_0_0", .id = DSC_0,
-		.base = 0x80000, .len = 0x4,
+		.base = 0x80000, .len = 0x10,
 		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL),
 		.sblk = &dsc_sblk_0,
 	},