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[v2,04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

Message ID	c5061fbe8ef9c4971cd45de7b5d8408dc1b848b4.1695189879.git.wangchen20@iscas.ac.cn
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com Cc: Chen Wang <wangchen20@iscas.ac.cn> Subject: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Date: Wed, 20 Sep 2023 14:38:08 +0800 Message-Id: <c5061fbe8ef9c4971cd45de7b5d8408dc1b848b4.1695189879.git.wangchen20@iscas.ac.cn> In-Reply-To: <cover.1695189879.git.wangchen20@iscas.ac.cn> References: <cover.1695189879.git.wangchen20@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add Milk-V Pioneer RISC-V board support \| [v2,00/11] Add Milk-V Pioneer RISC-V board support [v2,01/11] riscv: Add SOPHGO SOC family Kconfig support [v2,02/11] dt-bindings: vendor-prefixes: add milkv/sophgo [v2,03/11] dt-bindings: riscv: add sophgo sg2042 bindings [v2,04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles [v2,05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC [v2,06/11] dt-bindings: timer: Add Sophgo sg2042 clint [v2,07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts [v2,08/11] serial: 8250_dw: Add Sophgo SG2042 support [v2,09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree [v2,10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree [v2,11/11] riscv: defconfig: enable SOPHGO SoC

Commit Message

Chen Wang Sept. 20, 2023, 6:38 a.m. UTC

  The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

Comments

Conor Dooley Sept. 20, 2023, 8:37 a.m. UTC | #1

On Wed, Sep 20, 2023 at 02:38:08PM +0800, Chen Wang wrote:
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> 
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
>            - const: riscv
>        - items:
>            - enum:
> -- 
> 2.25.1
>

diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@  properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum: