Message ID | 20230919035343.1399389-8-apatel@ventanamicro.com |
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State | New |
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Mon, 18 Sep 2023 20:54:38 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id 3-20020a17090a034300b00273fc850342sm4000802pjf.20.2023.09.18.20.54.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 20:54:38 -0700 (PDT) From: Anup Patel <apatel@ventanamicro.com> To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Shuah Khan <shuah@kernel.org> Cc: Andrew Jones <ajones@ventanamicro.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test Date: Tue, 19 Sep 2023 09:23:43 +0530 Message-Id: <20230919035343.1399389-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919035343.1399389-1-apatel@ventanamicro.com> References: <20230919035343.1399389-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); 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Series |
KVM RISC-V Conditional Operations
|
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Commit Message
Anup Patel
Sept. 19, 2023, 3:53 a.m. UTC
We have a new conditional operations related ISA extensions so let us add
these extensions to get-reg-list test.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++
1 file changed, 4 insertions(+)
Comments
On Tue, Sep 19, 2023 at 09:23:43AM +0530, Anup Patel wrote: > We have a new conditional operations related ISA extensions so let us add > these extensions to get-reg-list test. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c > index 9f464c7996c6..4ad4bf87fa78 100644 > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c > @@ -50,6 +50,8 @@ bool filter_reg(__u64 reg) > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: > + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS: > + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: > return true; > /* AIA registers are always available when Ssaia can't be disabled */ > case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): > @@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id) > "KVM_RISCV_ISA_EXT_ZIFENCEI", > "KVM_RISCV_ISA_EXT_ZIHPM", > "KVM_RISCV_ISA_EXT_SMSTATEEN", > + "KVM_RISCV_ISA_EXT_XVENTANACONDOPS", > + "KVM_RISCV_ISA_EXT_ZICOND", > }; > > if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) { > -- > 2.34.1 > Don't we want to add test configs for these? Thanks, drew
On Wed, Sep 20, 2023 at 1:48 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Tue, Sep 19, 2023 at 09:23:43AM +0530, Anup Patel wrote: > > We have a new conditional operations related ISA extensions so let us add > > these extensions to get-reg-list test. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c > > index 9f464c7996c6..4ad4bf87fa78 100644 > > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c > > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c > > @@ -50,6 +50,8 @@ bool filter_reg(__u64 reg) > > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: > > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: > > case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: > > + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS: > > + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: > > return true; > > /* AIA registers are always available when Ssaia can't be disabled */ > > case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): > > @@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id) > > "KVM_RISCV_ISA_EXT_ZIFENCEI", > > "KVM_RISCV_ISA_EXT_ZIHPM", > > "KVM_RISCV_ISA_EXT_SMSTATEEN", > > + "KVM_RISCV_ISA_EXT_XVENTANACONDOPS", > > + "KVM_RISCV_ISA_EXT_ZICOND", > > }; > > > > if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) { > > -- > > 2.34.1 > > > > Don't we want to add test configs for these? Okay, I will update. Regards, Anup
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 9f464c7996c6..4ad4bf87fa78 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -50,6 +50,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: return true; /* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): @@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id) "KVM_RISCV_ISA_EXT_ZIFENCEI", "KVM_RISCV_ISA_EXT_ZIHPM", "KVM_RISCV_ISA_EXT_SMSTATEEN", + "KVM_RISCV_ISA_EXT_XVENTANACONDOPS", + "KVM_RISCV_ISA_EXT_ZICOND", }; if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {