diff mbox series

[v2,01/11] riscv: Add SOPHGO SOC family Kconfig support

Message ID	2c6db3d2db0d27d4b2b8364e0c03be3da292101e.1695189879.git.wangchen20@iscas.ac.cn
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com Cc: Chen Wang <wangchen20@iscas.ac.cn> Subject: [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Date: Wed, 20 Sep 2023 14:34:44 +0800 Message-Id: <2c6db3d2db0d27d4b2b8364e0c03be3da292101e.1695189879.git.wangchen20@iscas.ac.cn> In-Reply-To: <cover.1695189879.git.wangchen20@iscas.ac.cn> References: <cover.1695189879.git.wangchen20@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add Milk-V Pioneer RISC-V board support \| [v2,00/11] Add Milk-V Pioneer RISC-V board support [v2,01/11] riscv: Add SOPHGO SOC family Kconfig support [v2,02/11] dt-bindings: vendor-prefixes: add milkv/sophgo [v2,03/11] dt-bindings: riscv: add sophgo sg2042 bindings [v2,04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles [v2,05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC [v2,06/11] dt-bindings: timer: Add Sophgo sg2042 clint [v2,07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts [v2,08/11] serial: 8250_dw: Add Sophgo SG2042 support [v2,09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree [v2,10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree [v2,11/11] riscv: defconfig: enable SOPHGO SoC

Commit Message

Chen Wang Sept. 20, 2023, 6:34 a.m. UTC

  The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Guo Ren Sept. 20, 2023, 7:34 a.m. UTC | #1

On Wed, Sep 20, 2023 at 2:35 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/Kconfig.socs | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 6833d01e2e70..d4df7b5d0f16 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,11 @@ config SOC_SIFIVE
>         help
>           This enables support for SiFive SoC platform hardware.
>
> +config ARCH_SOPHGO
> +       bool "Sophgo SoCs"
> +       help
> +         This enables support for Sophgo SoC platform hardware.
> +
Reviewed-by: Guo Ren <guoren@kernel.org>

>  config ARCH_STARFIVE
>         def_bool SOC_STARFIVE
>
> --
> 2.25.1
>

Conor Dooley Sept. 20, 2023, 8:21 a.m. UTC | #2

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

diff mbox series

Patch

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..d4df7b5d0f16 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,11 @@  config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	help
+	  This enables support for Sophgo SoC platform hardware.
+
 config ARCH_STARFIVE
 	def_bool SOC_STARFIVE