diff mbox series

[04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles

Message ID	20230915072333.117991-1-wangchen20@iscas.ac.cn
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; From: Wang Chen <unicornxw@gmail.com> To: linux-riscv@lists.infradead.org, conor@kernel.org, aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, Wang Chen <wangchen20@iscas.ac.cn> Subject: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles Date: Fri, 15 Sep 2023 15:23:33 +0800 Message-Id: <20230915072333.117991-1-wangchen20@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	[01/12] riscv: Add SOPHGO SOC family Kconfig support \| [01/12] riscv: Add SOPHGO SOC family Kconfig support [02/12] dt-bindings: vendor-prefixes: add milkv/sophgo [03/12] dt-bindings: riscv: add sophgo sg2042 bindings [04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles [05/12] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC [06/12] dt-bindings: timer: Add Sophgo sg2042 clint [07/12] riscv: dts: add initial SOPHGO SG2042 SoC device tree [08/12] riscv: dts: sophgo: add Milk-V Pioneer board device tree [09/12] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts [10/12] serial: 8250_dw: Add Sophgo SG2042 support [11/12] riscv: dts: sophgo: Add sophgo,sg2024-uart compatibles [12/12] riscv: defconfig: enable SOPHGO SoC

Commit Message

Chen Wang Sept. 15, 2023, 7:23 a.m. UTC

  The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.

Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

Comments

Conor Dooley Sept. 15, 2023, 2:11 p.m. UTC | #1

On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> 
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

I figure this is missing a From: or Co-developed-by line.

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
>            - const: riscv
>        - items:
>            - enum:
> -- 
> 2.25.1
>

Chen Wang Sept. 16, 2023, 12:46 a.m. UTC | #2

Thanks for your detailed clarification, Rob. I'll pay attention next time.
Regards,

unicornx

Rob Herring <robh@kernel.org> 于2023年9月15日周五 23:03写道：
>
> On Fri, Sep 15, 2023 at 03:11:43PM +0100, Conor Dooley wrote:
> > On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> > > The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> > > Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> > >
> > > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> > > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> >
> > I figure this is missing a From: or Co-developed-by line.
>
> From: (author) as 2 authors for 1 line change is questionable.
>
> The sender's email should be the last S-o-b. So like this:
>
> From: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>
> ...
>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
>
>
> >
> > > ---
> > >  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index 38c0b5213736..185a0191bad6 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -47,6 +47,7 @@ properties:
> > >                - sifive,u74-mc
> > >                - thead,c906
> > >                - thead,c910
> > > +              - thead,c920
> > >            - const: riscv
> > >        - items:
> > >            - enum:
> > > --
> > > 2.25.1
> > >
>
>

diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@  properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum: