RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]
Checks
Commit Message
Fix bugzilla: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295
PR target/111295
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (insert_vsetvl):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr111295.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 3 +-
.../gcc.target/riscv/rvv/autovec/pr111295.c | 36 +++++++++++++++++++
2 files changed, 37 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
Comments
Committed, thanks Robin.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Robin Dapp via Gcc-patches
Sent: Wednesday, September 6, 2023 9:38 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com; kito.cheng@gmail.com
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]
OK.
Regards
Robin
@@ -721,8 +721,7 @@ insert_vsetvl (enum emit_type emit_type, rtx_insn *rinsn,
gcc_assert (has_vtype_op (rinsn) || vsetvl_insn_p (rinsn));
/* For user vsetvli a5, zero, we should use get_vl to get the VL
operand "a5". */
- rtx vl_op
- = vsetvl_insn_p (rinsn) ? get_vl (rinsn) : info.get_avl_reg_rtx ();
+ rtx vl_op = info.get_avl_or_vl_reg ();
gcc_assert (!vlmax_avl_p (vl_op));
emit_vsetvl_insn (VSETVL_NORMAL, emit_type, info, vl_op, rinsn);
return VSETVL_NORMAL;
new file mode 100644
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */
+
+#include <stdbool.h>
+int a, b, c, e, f, g, h, i, j, k;
+long l;
+int q ()
+{
+ int r ();
+ char *o, *d;
+ _Bool p = f;
+ while (g)
+ {
+ int m, n;
+ for (; m <= n; m++)
+ *d++ = m;
+ k = 1;
+ if (e)
+ break;
+ switch (*o)
+ {
+ case 'N':
+ o++;
+ if (c)
+ if (h)
+ while (i)
+ {
+ s (-l, ~0);
+ t (j);
+ d = d + (a & 10000000 ? u (r, 2) : b);
+ }
+ }
+ if (*o)
+ p ? s () : 0;
+ }
+}