diff mbox series

RISC-V:add a more appropriate type attribute

Message ID 20230823122843.23512-1-liaozhangjin@eswincomputing.com
State Unresolved
Headers
Series RISC-V:add a more appropriate type attribute |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Zhangjin Liao Aug. 23, 2023, 12:28 p.m. UTC 
  Due to the more accurate type attribute added to the clz, ctz, and pcnt operations
in https://github.com/gcc-mirror/gcc/commit/07e2576d6f3 the same type attribute
should be used here.

gcc/ChangeLog:

        * config/riscv/bitmanip.md:add a more appropriate type attribute
---
 gcc/config/riscv/bitmanip.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jeff Law Aug. 23, 2023, 2:04 p.m. UTC | #1 
On 8/23/23 06:28, Zhangjin Liao wrote:
> Due to the more accurate type attribute added to the clz, ctz, and pcnt operations
> inhttps://github.com/gcc-mirror/gcc/commit/07e2576d6f3  the same type attribute
> should be used here.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/bitmanip.md:add a more appropriate type attribute
Thanks.  I improved the ChangeLog slightly and pushed this to the trunk.

Jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 0c99152ffc8..7b55528ee49 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -262,7 +262,7 @@ 
           (match_operand:DI 2 "const_int_operand")))]
   "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)"
   "<bitmanip_insn>w\t%0,%1"
-  [(set_attr "type" "bitmanip")
+  [(set_attr "type" "<bitmanip_insn>")
    (set_attr "mode" "SI")])
 
 (define_insn "*<bitmanip_optab>di2"