diff mbox series

[v2] RISCV: Add rotate immediate regression test

Message ID 20230817011729.324315-1-patrick@rivosinc.com
State Accepted
Headers
Series [v2] RISCV: Add rotate immediate regression test |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Patrick O'Neill Aug. 17, 2023, 1:17 a.m. UTC 
  This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-rol-ror-08.c: New test.
	* gcc.target/riscv/zbb-rol-ror-09.c: New test.

Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
Trunk optimized these added testcases correctly.
GCC 13.2 and earlier do not optimize these cases correctly.

Expands on testcases added in:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c;h=0ccf520d349a82dafca0deb3d307a1080e8589a0
---
V2 Changes:
Move testcases to new files.
---
 .../gcc.target/riscv/zbb-rol-ror-08.c         | 25 +++++++++++++++++++
 .../gcc.target/riscv/zbb-rol-ror-09.c         | 15 +++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c

Comments

Jeff Law Aug. 17, 2023, 4:36 a.m. UTC | #1 
On 8/16/23 19:17, Patrick O'Neill wrote:
> This adds new regression tests to ensure half-register rotations are
> correctly optimized into rori instructions.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zbb-rol-ror-08.c: New test.
> 	* gcc.target/riscv/zbb-rol-ror-09.c: New test.
> 
> Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
> Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
OK
jeff
Patrick O'Neill Aug. 17, 2023, 5:10 p.m. UTC | #2 
On 8/16/23 21:36, Jeff Law wrote:

>
>
> On 8/16/23 19:17, Patrick O'Neill wrote:
>> This adds new regression tests to ensure half-register rotations are
>> correctly optimized into rori instructions.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/zbb-rol-ror-08.c: New test.
>>     * gcc.target/riscv/zbb-rol-ror-09.c: New test.
>>
>> Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
>> Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
> OK
> jeff
Committed
Patrick
Palmer Dabbelt Aug. 17, 2023, 5:40 p.m. UTC | #3 
On Thu, 17 Aug 2023 10:10:38 PDT (-0700), Patrick O'Neill wrote:
> On 8/16/23 21:36, Jeff Law wrote:
>
>>
>>
>> On 8/16/23 19:17, Patrick O'Neill wrote:
>>> This adds new regression tests to ensure half-register rotations are
>>> correctly optimized into rori instructions.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>>     * gcc.target/riscv/zbb-rol-ror-08.c: New test.
>>>     * gcc.target/riscv/zbb-rol-ror-09.c: New test.
>>>
>>> Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
>>> Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
>> OK
>> jeff
> Committed

IIRC this came up in the context of Linux's TCP checksum code.

> Patrick
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
new file mode 100644
index 00000000000..30696f3bb32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+**	rori	a0,a0,32
+**	ret
+*/
+unsigned long foo1(unsigned long rotate)
+{
+    return (rotate << 32) | (rotate >> 32);
+}
+
+/*
+**foo2:
+**	roriw	a0,a0,16
+**	ret
+*/
+unsigned int foo2(unsigned int rotate)
+{
+    return (rotate << 16) | (rotate >> 16);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
new file mode 100644
index 00000000000..a3054553e18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+/*
+**foo1:
+**	rori	a0,a0,16
+**	ret
+*/
+unsigned int foo1(unsigned int rs1)
+{
+    return (rs1 << 16) | (rs1 >> 16);
+}