[v1] RISC-V: Support RVV VFWREDOSUM.VS rounding mode intrinsic API

  From: Pan Li <pan2.li@intel.com>

This patch would like to support the rounding mode API for the
VFWREDOSUM.VS as the below samples

* __riscv_vfwredosum_vs_f32m1_f64m1_rm
* __riscv_vfwredosum_vs_f32m1_f64m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(widen_freducop): Add frm_opt_type template arg.
	(vfwredosum_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfwredosum_frm): New intrinsic function def.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-wredosum.c: New test.
---
 .../riscv/riscv-vector-builtins-bases.cc      |  9 ++++-
 .../riscv/riscv-vector-builtins-bases.h       |  1 +
 .../riscv/riscv-vector-builtins-functions.def |  2 ++
 .../riscv/rvv/base/float-point-wredosum.c     | 33 +++++++++++++++++++
 4 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
  

ok

On Thu, Aug 17, 2023 at 3:26 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to support the rounding mode API for the
> VFWREDOSUM.VS as the below samples
>
> * __riscv_vfwredosum_vs_f32m1_f64m1_rm
> * __riscv_vfwredosum_vs_f32m1_f64m1_rm_m
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vector-builtins-bases.cc
>         (widen_freducop): Add frm_opt_type template arg.
>         (vfwredosum_frm_obj): New declaration.
>         (BASE): Ditto.
>         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
>         * config/riscv/riscv-vector-builtins-functions.def
>         (vfwredosum_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/float-point-wredosum.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc      |  9 ++++-
>  .../riscv/riscv-vector-builtins-bases.h       |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  2 ++
>  .../riscv/rvv/base/float-point-wredosum.c     | 33 +++++++++++++++++++
>  4 files changed, 44 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index ef2991359da..abf03bab0da 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1866,10 +1866,15 @@ public:
>  };
>
>  /* Implements widening floating-point reduction instructions.  */
> -template<int UNSPEC>
> +template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM>
>  class widen_freducop : public function_base
>  {
>  public:
> +  bool has_rounding_mode_operand_p () const override
> +  {
> +    return FRM_OP == HAS_FRM;
> +  }
> +
>    bool apply_mask_policy_p () const override { return false; }
>
>    rtx expand (function_expander &e) const override
> @@ -2544,6 +2549,7 @@ static CONSTEXPR const reducop<SMAX> vfredmax_obj;
>  static CONSTEXPR const reducop<SMIN> vfredmin_obj;
>  static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj;
>  static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj;
> +static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj;
>  static CONSTEXPR const vmv vmv_x_obj;
>  static CONSTEXPR const vmv_s vmv_s_obj;
>  static CONSTEXPR const vmv vfmv_f_obj;
> @@ -2802,6 +2808,7 @@ BASE (vfredosum_frm)
>  BASE (vfredmax)
>  BASE (vfredmin)
>  BASE (vfwredosum)
> +BASE (vfwredosum_frm)
>  BASE (vfwredusum)
>  BASE (vmv_x)
>  BASE (vmv_s)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index da8412b66df..c1bb164a712 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -245,6 +245,7 @@ extern const function_base *const vfredosum_frm;
>  extern const function_base *const vfredmax;
>  extern const function_base *const vfredmin;
>  extern const function_base *const vfwredosum;
> +extern const function_base *const vfwredosum_frm;
>  extern const function_base *const vfwredusum;
>  extern const function_base *const vmv_x;
>  extern const function_base *const vmv_s;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 80e65bfb14b..da1157f5a56 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -507,6 +507,8 @@ DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
>  DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
>  DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops)
>
> +DEF_RVV_FUNCTION (vfwredosum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops)
> +
>  /* 15. Vector Mask Instructions.  */
>
>  // 15.1. Vector Mask-Register Logical Instructions
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
> new file mode 100644
> index 00000000000..acf79569a22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
> @@ -0,0 +1,33 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat64m1_t
> +test_riscv_vfwredosum_vs_f32m1_f64m1_rm (vfloat32m1_t op1, vfloat64m1_t op2,
> +                                        size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1_rm (op1, op2, 0, vl);
> +}
> +
> +vfloat64m1_t
> +test_vfwredosum_vs_f32m1_f64m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
> +                                    vfloat64m1_t op2, size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1_rm_m (mask, op1, op2, 1, vl);
> +}
> +
> +vfloat64m1_t
> +test_riscv_vfwredosum_vs_f32m1_f64m1 (vfloat32m1_t op1, vfloat64m1_t op2,
> +                                     size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1 (op1, op2, vl);
> +}
> +
> +vfloat64m1_t
> +test_vfwredosum_vs_f32m1_f64m1_m (vbool32_t mask, vfloat32m1_t op1,
> +                                 vfloat64m1_t op2, size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1_m (mask, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
> --
> 2.34.1
>