RISC-V: Support TU for integer ternary OP[PR110964]
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Commit Message
PR target/110964
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_cond_len_ternop): Add integer ternary.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr110964.c: New test.
---
gcc/config/riscv/riscv-v.cc | 3 +--
.../gcc.target/riscv/rvv/autovec/pr110964.c | 13 +++++++++++++
2 files changed, 14 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
Comments
Committed, thanks Robin.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Robin Dapp via Gcc-patches
Sent: Thursday, August 10, 2023 8:09 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; kito.cheng@gmail.com; kito.cheng@sifive.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH] RISC-V: Support TU for integer ternary OP[PR110964]
OK.
Regards
Robin
@@ -3604,8 +3604,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
if (FLOAT_MODE_P (mode))
emit_nonvlmax_fp_ternary_tu_insn (icode, RVV_TERNOP_TU, ops, len);
else
- /* FIXME: Enable this case when we support it in the middle-end. */
- gcc_unreachable ();
+ emit_nonvlmax_tu_insn (icode, RVV_TERNOP_TU, ops, len);
}
else
{
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */
+
+int *a;
+long b, c;
+
+int d ()
+{
+ const int e;
+ for (; a < e; a++) /* { dg-warning "comparison between pointer and integer" } */
+ c += *a * b;
+}
+