[v2,05/23] arm64: dts: Update cache properties for arm
Commit Message
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++
arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++
arch/arm64/boot/dts/arm/juno.dts | 2 ++
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
7 files changed, 10 insertions(+)
Comments
On Mon, 7 Nov 2022 16:56:53 +0100, Pierre Gondois wrote:
> v2:
> - Update/Add patches for missed cache properties requiring to be
> updated for the following platforns: bcm, amazon, arm, exynos,
> freescale, marvell, mediatek, nvidia, socinext, tesla, ti.
> Missed cache properties were detected using Rob Herring's branch:
> https://github.com/robherring/dt-schema/tree/cache-rework
> - v1 of exynos, tesla were merged.
> - Updated wrong reference in commit message.
> - Added received Rb/Acked-by.
>
> [...]
Applied to sudeep.holla/linux (for-next/juno), thanks!
[05/23] arm64: dts: Update cache properties for arm
https://git.kernel.org/sudeep.holla/c/59fb813f9742
--
Regards,
Sudeep
@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
@@ -58,6 +58,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -189,6 +189,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -195,6 +195,7 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -194,6 +194,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -71,6 +71,7 @@ cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -57,6 +57,7 @@ cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};