[2/3] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions

Message ID 20230801085352.22873-3-quic_luoj@quicinc.com
State New
Headers
Series add clock controller of qca8386/qca8084 |

Commit Message

Jie Luo Aug. 1, 2023, 8:53 a.m. UTC
  QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 .../bindings/clock/qcom,nsscc-qca8k.yaml      |  59 ++++++++++
 include/dt-bindings/clock/qcom,nsscc-qca8k.h  | 102 ++++++++++++++++++
 include/dt-bindings/reset/qcom,nsscc-qca8k.h  |  76 +++++++++++++
 3 files changed, 237 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
 create mode 100644 include/dt-bindings/clock/qcom,nsscc-qca8k.h
 create mode 100644 include/dt-bindings/reset/qcom,nsscc-qca8k.h
  

Comments

Krzysztof Kozlowski Aug. 7, 2023, 6:52 a.m. UTC | #1
On 01/08/2023 10:53, Luo Jie wrote:
> QCA8386/QCA8084 includes the clock & reset controller that is
> accessed by MDIO bus. Two work modes are supported, qca8386 works
> as switch mode, qca8084 works as PHY mode.
> 
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  .../bindings/clock/qcom,nsscc-qca8k.yaml      |  59 ++++++++++
>  include/dt-bindings/clock/qcom,nsscc-qca8k.h  | 102 ++++++++++++++++++
>  include/dt-bindings/reset/qcom,nsscc-qca8k.h  |  76 +++++++++++++
>  3 files changed, 237 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,nsscc-qca8k.h
>  create mode 100644 include/dt-bindings/reset/qcom,nsscc-qca8k.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
> new file mode 100644
> index 000000000000..8fb77156070c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,nsscc-qca8k.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
> +
> +maintainers:
> +  - Luo Jie <quic_luoj@quicinc.com>
> +
> +description: |
> +  Qualcomm NSS clock control module provides the clocks and resets
> +  on QCA8386(switch mode)/QCA8084(PHY mode)
> +
> +  See also::
> +    include/dt-bindings/clock/qcom,nsscc-qca8k.h
> +    include/dt-bindings/reset/qcom,nsscc-qca8k.h
> +
> +properties:
> +  compatible:
> +    const: qcom,nsscc-qca8k

SoC name is before IP block names. See:
Documentation/devicetree/bindings/arm/qcom-soc.yaml

qca8k is not SoC specific. I don't know what you are documenting here,
but if this is a SoC, then follow SoC rules.

If this is not SoC, it confuses me a bit to use GCC binding.

Anyway, this was not tested, as pointed out by bot... Please test the
code before sending.

Best regards,
Krzysztof
  
Jie Luo Aug. 8, 2023, 5:19 a.m. UTC | #2
On 8/7/2023 2:52 PM, Krzysztof Kozlowski wrote:
> On 01/08/2023 10:53, Luo Jie wrote:
>> QCA8386/QCA8084 includes the clock & reset controller that is
>> accessed by MDIO bus. Two work modes are supported, qca8386 works
>> as switch mode, qca8084 works as PHY mode.
>>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   .../bindings/clock/qcom,nsscc-qca8k.yaml      |  59 ++++++++++
>>   include/dt-bindings/clock/qcom,nsscc-qca8k.h  | 102 ++++++++++++++++++
>>   include/dt-bindings/reset/qcom,nsscc-qca8k.h  |  76 +++++++++++++
>>   3 files changed, 237 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
>>   create mode 100644 include/dt-bindings/clock/qcom,nsscc-qca8k.h
>>   create mode 100644 include/dt-bindings/reset/qcom,nsscc-qca8k.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
>> new file mode 100644
>> index 000000000000..8fb77156070c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
>> @@ -0,0 +1,59 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,nsscc-qca8k.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
>> +
>> +maintainers:
>> +  - Luo Jie <quic_luoj@quicinc.com>
>> +
>> +description: |
>> +  Qualcomm NSS clock control module provides the clocks and resets
>> +  on QCA8386(switch mode)/QCA8084(PHY mode)
>> +
>> +  See also::
>> +    include/dt-bindings/clock/qcom,nsscc-qca8k.h
>> +    include/dt-bindings/reset/qcom,nsscc-qca8k.h
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,nsscc-qca8k
> 
> SoC name is before IP block names. See:
> Documentation/devicetree/bindings/arm/qcom-soc.yaml
> 
> qca8k is not SoC specific. I don't know what you are documenting here,
> but if this is a SoC, then follow SoC rules.
> 
> If this is not SoC, it confuses me a bit to use GCC binding.
> 
> Anyway, this was not tested, as pointed out by bot... Please test the
> code before sending.
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,

Thanks for the review comments.
qca8383/qca8084 is a network chip that support switch mode and PHY mode,
the hardware register is accessed by MDIO bus, which is not a SOC.

But it has the self-contained clock controller system, the clock 
framework of qca8386/qca8084 is same as the GCC of ipq platform such as 
ipq9574.

would you help advise whether we can document it with the compatible
"qcom,qca8k-nsscc"?

Jie.
  
Krzysztof Kozlowski Aug. 8, 2023, 5:57 a.m. UTC | #3
On 08/08/2023 07:19, Jie Luo wrote:
>>> +properties:
>>> +  compatible:
>>> +    const: qcom,nsscc-qca8k
>>
>> SoC name is before IP block names. See:
>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>
>> qca8k is not SoC specific. I don't know what you are documenting here,
>> but if this is a SoC, then follow SoC rules.
>>
>> If this is not SoC, it confuses me a bit to use GCC binding.
>>
>> Anyway, this was not tested, as pointed out by bot... Please test the
>> code before sending.
>>
>> Best regards,
>> Krzysztof
>>
> 
> Hi Krzysztof,
> 
> Thanks for the review comments.
> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
> the hardware register is accessed by MDIO bus, which is not a SOC.
> 
> But it has the self-contained clock controller system, the clock 
> framework of qca8386/qca8084 is same as the GCC of ipq platform such as 
> ipq9574.

OK

> 
> would you help advise whether we can document it with the compatible
> "qcom,qca8k-nsscc"?

For example:
qcom,qca8084-nsscc

Best regards,
Krzysztof
  
Jie Luo Aug. 8, 2023, 6:31 a.m. UTC | #4
On 8/8/2023 1:57 PM, Krzysztof Kozlowski wrote:
> On 08/08/2023 07:19, Jie Luo wrote:
>>>> +properties:
>>>> +  compatible:
>>>> +    const: qcom,nsscc-qca8k
>>>
>>> SoC name is before IP block names. See:
>>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>>
>>> qca8k is not SoC specific. I don't know what you are documenting here,
>>> but if this is a SoC, then follow SoC rules.
>>>
>>> If this is not SoC, it confuses me a bit to use GCC binding.
>>>
>>> Anyway, this was not tested, as pointed out by bot... Please test the
>>> code before sending.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Hi Krzysztof,
>>
>> Thanks for the review comments.
>> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
>> the hardware register is accessed by MDIO bus, which is not a SOC.
>>
>> But it has the self-contained clock controller system, the clock
>> framework of qca8386/qca8084 is same as the GCC of ipq platform such as
>> ipq9574.
> 
> OK
> 
>>
>> would you help advise whether we can document it with the compatible
>> "qcom,qca8k-nsscc"?
> 
> For example:
> qcom,qca8084-nsscc
> 
> Best regards,
> Krzysztof
> 
Thanks Krzysztof for the suggestion.

i will document the compatible below.
"qcom,qca8084-nsscc" for the PHY mode of device.
"qcom,qca8386-nsscc" for the switch mode of device.

Jie.
  
Krzysztof Kozlowski Aug. 8, 2023, 6:46 a.m. UTC | #5
On 08/08/2023 08:31, Jie Luo wrote:
> 
> 
> On 8/8/2023 1:57 PM, Krzysztof Kozlowski wrote:
>> On 08/08/2023 07:19, Jie Luo wrote:
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    const: qcom,nsscc-qca8k
>>>>
>>>> SoC name is before IP block names. See:
>>>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>>>
>>>> qca8k is not SoC specific. I don't know what you are documenting here,
>>>> but if this is a SoC, then follow SoC rules.
>>>>
>>>> If this is not SoC, it confuses me a bit to use GCC binding.
>>>>
>>>> Anyway, this was not tested, as pointed out by bot... Please test the
>>>> code before sending.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> Hi Krzysztof,
>>>
>>> Thanks for the review comments.
>>> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
>>> the hardware register is accessed by MDIO bus, which is not a SOC.
>>>
>>> But it has the self-contained clock controller system, the clock
>>> framework of qca8386/qca8084 is same as the GCC of ipq platform such as
>>> ipq9574.
>>
>> OK
>>
>>>
>>> would you help advise whether we can document it with the compatible
>>> "qcom,qca8k-nsscc"?
>>
>> For example:
>> qcom,qca8084-nsscc
>>
>> Best regards,
>> Krzysztof
>>
> Thanks Krzysztof for the suggestion.
> 
> i will document the compatible below.
> "qcom,qca8084-nsscc" for the PHY mode of device.
> "qcom,qca8386-nsscc" for the switch mode of device.

The clocks seem to be exactly the same for both, so use only one
compatible in the driver (the fallback) and oneOf in the bindings like:

https://elixir.bootlin.com/linux/v6.3-rc6/source/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml#L31

Best regards,
Krzysztof
  
Jie Luo Aug. 8, 2023, 6:59 a.m. UTC | #6
On 8/8/2023 2:46 PM, Krzysztof Kozlowski wrote:
> On 08/08/2023 08:31, Jie Luo wrote:
>>
>>
>> On 8/8/2023 1:57 PM, Krzysztof Kozlowski wrote:
>>> On 08/08/2023 07:19, Jie Luo wrote:
>>>>>> +properties:
>>>>>> +  compatible:
>>>>>> +    const: qcom,nsscc-qca8k
>>>>>
>>>>> SoC name is before IP block names. See:
>>>>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>>>>
>>>>> qca8k is not SoC specific. I don't know what you are documenting here,
>>>>> but if this is a SoC, then follow SoC rules.
>>>>>
>>>>> If this is not SoC, it confuses me a bit to use GCC binding.
>>>>>
>>>>> Anyway, this was not tested, as pointed out by bot... Please test the
>>>>> code before sending.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Hi Krzysztof,
>>>>
>>>> Thanks for the review comments.
>>>> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
>>>> the hardware register is accessed by MDIO bus, which is not a SOC.
>>>>
>>>> But it has the self-contained clock controller system, the clock
>>>> framework of qca8386/qca8084 is same as the GCC of ipq platform such as
>>>> ipq9574.
>>>
>>> OK
>>>
>>>>
>>>> would you help advise whether we can document it with the compatible
>>>> "qcom,qca8k-nsscc"?
>>>
>>> For example:
>>> qcom,qca8084-nsscc
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Thanks Krzysztof for the suggestion.
>>
>> i will document the compatible below.
>> "qcom,qca8084-nsscc" for the PHY mode of device.
>> "qcom,qca8386-nsscc" for the switch mode of device.
> 
> The clocks seem to be exactly the same for both, so use only one
> compatible in the driver (the fallback) and oneOf in the bindings like:
> 
> https://elixir.bootlin.com/linux/v6.3-rc6/source/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml#L31
> 
> Best regards,
> Krzysztof
> 
Yes, it is the same driver for both.
i will update this in the next patch set, thanks Krzysztof.

Jie.
  

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
new file mode 100644
index 000000000000..8fb77156070c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
@@ -0,0 +1,59 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nsscc-qca8k.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
+
+maintainers:
+  - Luo Jie <quic_luoj@quicinc.com>
+
+description: |
+  Qualcomm NSS clock control module provides the clocks and resets
+  on QCA8386(switch mode)/QCA8084(PHY mode)
+
+  See also::
+    include/dt-bindings/clock/qcom,nsscc-qca8k.h
+    include/dt-bindings/reset/qcom,nsscc-qca8k.h
+
+properties:
+  compatible:
+    const: qcom,nsscc-qca8k
+
+  clocks:
+    items:
+      - description: Chip XO source
+      - description: UNIPHY1 RX 312P5M clock source
+      - description: UNIPHY1 TX 312P5M clock source
+
+  reg:
+    items:
+      - description: MDIO bus address for Clock & Reset Controller register
+
+required:
+  - compatible
+  - clocks
+  - reg
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    clock-controller@24 {
+      compatible = "qcom,nsscc-qca8k";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      reg = <24>;
+      clocks = <&qca8k_xo>,
+               <0>,
+               <0>,
+               <0>,
+               <0>,
+               <&qca8k_uniphy1_rx312p5m>,
+               <&qca8k_uniphy1_tx312p5m>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,nsscc-qca8k.h b/include/dt-bindings/clock/qcom,nsscc-qca8k.h
new file mode 100644
index 000000000000..3f49147aacc5
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nsscc-qca8k.h
@@ -0,0 +1,102 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_QCA8K_H
+#define _DT_BINDINGS_CLK_QCOM_NSS_CC_QCA8K_H
+
+#define NSS_CC_SWITCH_CORE_CLK_SRC				0
+#define NSS_CC_SWITCH_CORE_CLK					1
+#define NSS_CC_APB_BRIDGE_CLK					2
+#define NSS_CC_MAC0_TX_CLK_SRC					3
+#define NSS_CC_MAC0_TX_DIV_CLK_SRC				4
+#define NSS_CC_MAC0_TX_CLK					5
+#define NSS_CC_MAC0_TX_SRDS1_CLK				6
+#define NSS_CC_MAC0_RX_CLK_SRC					7
+#define NSS_CC_MAC0_RX_DIV_CLK_SRC				8
+#define NSS_CC_MAC0_RX_CLK					9
+#define NSS_CC_MAC0_RX_SRDS1_CLK				10
+#define NSS_CC_MAC1_TX_CLK_SRC					11
+#define NSS_CC_MAC1_TX_DIV_CLK_SRC				12
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC		13
+#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK				14
+#define NSS_CC_MAC1_TX_CLK					15
+#define NSS_CC_MAC1_GEPHY0_TX_CLK				16
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK			17
+#define NSS_CC_MAC1_RX_CLK_SRC					18
+#define NSS_CC_MAC1_RX_DIV_CLK_SRC				19
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC		20
+#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK				21
+#define NSS_CC_MAC1_RX_CLK					22
+#define NSS_CC_MAC1_GEPHY0_RX_CLK				23
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK			24
+#define NSS_CC_MAC2_TX_CLK_SRC					25
+#define NSS_CC_MAC2_TX_DIV_CLK_SRC				26
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC		27
+#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK				28
+#define NSS_CC_MAC2_TX_CLK					29
+#define NSS_CC_MAC2_GEPHY1_TX_CLK				30
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK			31
+#define NSS_CC_MAC2_RX_CLK_SRC					32
+#define NSS_CC_MAC2_RX_DIV_CLK_SRC				33
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC		34
+#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK				35
+#define NSS_CC_MAC2_RX_CLK					36
+#define NSS_CC_MAC2_GEPHY1_RX_CLK				37
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK			38
+#define NSS_CC_MAC3_TX_CLK_SRC					39
+#define NSS_CC_MAC3_TX_DIV_CLK_SRC				40
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC		41
+#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK				42
+#define NSS_CC_MAC3_TX_CLK					43
+#define NSS_CC_MAC3_GEPHY2_TX_CLK				44
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK			45
+#define NSS_CC_MAC3_RX_CLK_SRC					46
+#define NSS_CC_MAC3_RX_DIV_CLK_SRC				47
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC		48
+#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK				49
+#define NSS_CC_MAC3_RX_CLK					50
+#define NSS_CC_MAC3_GEPHY2_RX_CLK				51
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK			52
+#define NSS_CC_MAC4_TX_CLK_SRC					53
+#define NSS_CC_MAC4_TX_DIV_CLK_SRC				54
+#define NSS_CC_MAC4_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC		55
+#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK				56
+#define NSS_CC_MAC4_TX_CLK					57
+#define NSS_CC_MAC4_GEPHY3_TX_CLK				58
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK			59
+#define NSS_CC_MAC4_RX_CLK_SRC					60
+#define NSS_CC_MAC4_RX_DIV_CLK_SRC				61
+#define NSS_CC_MAC4_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC		62
+#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK				63
+#define NSS_CC_MAC4_RX_CLK					64
+#define NSS_CC_MAC4_GEPHY3_RX_CLK				65
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK			66
+#define NSS_CC_MAC5_TX_CLK_SRC					67
+#define NSS_CC_MAC5_TX_DIV_CLK_SRC				68
+#define NSS_CC_MAC5_TX_SRDS0_CLK				69
+#define NSS_CC_MAC5_TX_CLK					70
+#define NSS_CC_MAC5_RX_CLK_SRC					71
+#define NSS_CC_MAC5_RX_DIV_CLK_SRC				72
+#define NSS_CC_MAC5_RX_SRDS0_CLK				73
+#define NSS_CC_MAC5_RX_CLK					74
+#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC				75
+#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC				76
+#define NSS_CC_AHB_CLK_SRC					77
+#define NSS_CC_AHB_CLK						78
+#define NSS_CC_SEC_CTRL_AHB_CLK					79
+#define NSS_CC_TLMM_CLK						80
+#define NSS_CC_TLMM_AHB_CLK					81
+#define NSS_CC_CNOC_AHB_CLK					82
+#define NSS_CC_MDIO_AHB_CLK					83
+#define NSS_CC_MDIO_MASTER_AHB_CLK				84
+#define NSS_CC_SYS_CLK_SRC					85
+#define NSS_CC_SRDS0_SYS_CLK					86
+#define NSS_CC_SRDS1_SYS_CLK					87
+#define NSS_CC_GEPHY0_SYS_CLK					88
+#define NSS_CC_GEPHY1_SYS_CLK					89
+#define NSS_CC_GEPHY2_SYS_CLK					90
+#define NSS_CC_GEPHY3_SYS_CLK					91
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,nsscc-qca8k.h b/include/dt-bindings/reset/qcom,nsscc-qca8k.h
new file mode 100644
index 000000000000..1bc763f52333
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,nsscc-qca8k.h
@@ -0,0 +1,76 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_NSS_CC_QCA8K_H
+#define _DT_BINDINGS_RESET_QCOM_NSS_CC_QCA8K_H
+
+#define NSS_CC_SWITCH_CORE_ARES				1
+#define NSS_CC_APB_BRIDGE_ARES				2
+#define NSS_CC_MAC0_TX_ARES				3
+#define NSS_CC_MAC0_TX_SRDS1_ARES			4
+#define NSS_CC_MAC0_RX_ARES				5
+#define NSS_CC_MAC0_RX_SRDS1_ARES			6
+#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES			7
+#define NSS_CC_MAC1_TX_ARES				8
+#define NSS_CC_MAC1_GEPHY0_TX_ARES			9
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES		10
+#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES			11
+#define NSS_CC_MAC1_RX_ARES				12
+#define NSS_CC_MAC1_GEPHY0_RX_ARES			13
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES		14
+#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES			15
+#define NSS_CC_MAC2_TX_ARES				16
+#define NSS_CC_MAC2_GEPHY1_TX_ARES			17
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES		18
+#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES			19
+#define NSS_CC_MAC2_RX_ARES				20
+#define NSS_CC_MAC2_GEPHY1_RX_ARES			21
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES		22
+#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES			23
+#define NSS_CC_MAC3_TX_ARES				24
+#define NSS_CC_MAC3_GEPHY2_TX_ARES			25
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES		26
+#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES			27
+#define NSS_CC_MAC3_RX_ARES				28
+#define NSS_CC_MAC3_GEPHY2_RX_ARES			29
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES		30
+#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES			31
+#define NSS_CC_MAC4_TX_ARES				32
+#define NSS_CC_MAC4_GEPHY3_TX_ARES			33
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES		34
+#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES			35
+#define NSS_CC_MAC4_RX_ARES				36
+#define NSS_CC_MAC4_GEPHY3_RX_ARES			37
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES		38
+#define NSS_CC_MAC5_TX_ARES				39
+#define NSS_CC_MAC5_TX_SRDS0_ARES			40
+#define NSS_CC_MAC5_RX_ARES				41
+#define NSS_CC_MAC5_RX_SRDS0_ARES			42
+#define NSS_CC_AHB_ARES					43
+#define NSS_CC_SEC_CTRL_AHB_ARES			44
+#define NSS_CC_TLMM_ARES				45
+#define NSS_CC_TLMM_AHB_ARES				46
+#define NSS_CC_CNOC_AHB_ARES				47
+#define NSS_CC_MDIO_AHB_ARES				48
+#define NSS_CC_MDIO_MASTER_AHB_ARES			49
+#define NSS_CC_SRDS0_SYS_ARES				50
+#define NSS_CC_SRDS1_SYS_ARES				51
+#define NSS_CC_GEPHY0_SYS_ARES				52
+#define NSS_CC_GEPHY1_SYS_ARES				53
+#define NSS_CC_GEPHY2_SYS_ARES				54
+#define NSS_CC_GEPHY3_SYS_ARES				55
+#define NSS_CC_SEC_CTRL_ARES				56
+#define NSS_CC_SEC_CTRL_SENSE_ARES			57
+#define NSS_CC_SLEEP_ARES				58
+#define NSS_CC_DEBUG_ARES				59
+#define NSS_CC_GEPHY0_ARES				60
+#define NSS_CC_GEPHY1_ARES				61
+#define NSS_CC_GEPHY2_ARES				62
+#define NSS_CC_GEPHY3_ARES				63
+#define NSS_CC_DSP_ARES					64
+#define NSS_CC_GLOBAL_ARES				65
+#define NSS_CC_XPCS_ARES				66
+
+#endif