Message ID | 20230805045554.786092-1-d-gole@ti.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g16-20020a056a000b9000b006738dfbaf42si2949135pfj.374.2023.08.05.01.39.56; Sat, 05 Aug 2023 01:40:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="F6HY88Q/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229544AbjHEE5x (ORCPT <rfc822;liqunnana@gmail.com> + 99 others); Sat, 5 Aug 2023 00:57:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbjHEE5s (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Sat, 5 Aug 2023 00:57:48 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E17AE11B; Fri, 4 Aug 2023 21:57:44 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3754va3Z093118; Fri, 4 Aug 2023 23:57:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691211456; bh=LbPx6unMfm99M2erei+3z5Fvj12KtkSdmpVzoBEKAP4=; h=From:To:CC:Subject:Date; b=F6HY88Q/MB9BqA7CYkjDDk1/vLCClp1nmhy3rvUMXCiKrSN8sM1AMNkOlxK+qKfl/ jhOAvvY2AdciDYkHYOx/6AKTCuqsawTd59vmxiWiCcx2rgACAuZi8qx1ougVQGhnc4 rzPqyVAOtSWFAlfSPXa9SUvF3zp6g08qnNX08g4g= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3754vaWG056991 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Aug 2023 23:57:36 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 4 Aug 2023 23:57:36 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 4 Aug 2023 23:57:36 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3754vZ2l095184; Fri, 4 Aug 2023 23:57:36 -0500 From: Dhruva Gole <d-gole@ti.com> To: Tony Lindgren <tony@atomide.com>, Linus Walleij <linus.walleij@linaro.org> CC: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-omap@vger.kernel.org>, <linux-gpio@vger.kernel.org>, Dhruva Gole <d-gole@ti.com>, Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com> Subject: [PATCH] pinctrl: single: Add compatible for ti,am625-padconf Date: Sat, 5 Aug 2023 10:25:55 +0530 Message-ID: <20230805045554.786092-1-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773377746060233378 X-GMAIL-MSGID: 1773377746060233378 |
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pinctrl: single: Add compatible for ti,am625-padconf
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Commit Message
Dhruva Gole
Aug. 5, 2023, 4:55 a.m. UTC
From: Tony Lindgren <tony@atomide.com> Add compatible for ti,am625-padconf to enable the use of wake-up events. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> --- Base: ***** tag: next-20230731 + below "depends on" patches Depends on: *********** [0] Update pinctrl-single to use yaml [1] dt-binding: pinctrl-single: add am625 compatible Links: ****** [0] https://lore.kernel.org/linux-omap/20230731061908.GG5194@atomide.com/T/ [1] https://lore.kernel.org/all/20230804050737.635186-1-d-gole@ti.com/ Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Link to this patch: ****************** https://lore.kernel.org/all/20230805045554.786092-1-d-gole@ti.com drivers/pinctrl/pinctrl-single.c | 7 +++++++ 1 file changed, 7 insertions(+)
Comments
On 10:25-20230805, Dhruva Gole wrote: > From: Tony Lindgren <tony@atomide.com> > > Add compatible for ti,am625-padconf to enable the use of wake-up events. > > Signed-off-by: Tony Lindgren <tony@atomide.com> > Signed-off-by: Dhruva Gole <d-gole@ti.com> > --- > > Base: > ***** > tag: next-20230731 + below "depends on" patches > > Depends on: > *********** > [0] Update pinctrl-single to use yaml > [1] dt-binding: pinctrl-single: add am625 compatible > > Links: > ****** > [0] https://lore.kernel.org/linux-omap/20230731061908.GG5194@atomide.com/T/ > [1] https://lore.kernel.org/all/20230804050737.635186-1-d-gole@ti.com/ > > Cc: Nishanth Menon <nm@ti.com> > Cc: Vignesh Raghavendra <vigneshr@ti.com> > > Link to this patch: > ****************** > https://lore.kernel.org/all/20230805045554.786092-1-d-gole@ti.com > > drivers/pinctrl/pinctrl-single.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c > index f056923ecc98..3a2a9910f2ec 100644 > --- a/drivers/pinctrl/pinctrl-single.c > +++ b/drivers/pinctrl/pinctrl-single.c > @@ -1954,6 +1954,12 @@ static const struct pcs_soc_data pinctrl_single_am437x = { > .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ > }; > > +static const struct pcs_soc_data pinctrl_single_am625 = { > + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, > + .irq_enable_mask = (1 << 29), /* WKUP_EN */ > + .irq_status_mask = (1 << 30), /* WKUP_EVT */ > +}; > + Why cant we set this in the k3-pinctrl.h and set it once? The event will not be generated until wakeup daisy chain is triggered anyways. Have you looked at all the padconf registers across devices to ensure the WKUP_EN/EVT bits are present? daisy chain feature is used elsewhere as well. > static const struct pcs_soc_data pinctrl_single = { > }; > > @@ -1962,6 +1968,7 @@ static const struct pcs_soc_data pinconf_single = { > }; > > static const struct of_device_id pcs_of_match[] = { > + { .compatible = "ti,am625-padconf", .data = &pinctrl_single_am625 }, > { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, > { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, > { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, > -- > 2.34.1 >
* Nishanth Menon <nm@ti.com> [230805 17:15]: > On 10:25-20230805, Dhruva Gole wrote: > > From: Tony Lindgren <tony@atomide.com> > > +static const struct pcs_soc_data pinctrl_single_am625 = { > > + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, > > + .irq_enable_mask = (1 << 29), /* WKUP_EN */ > > + .irq_status_mask = (1 << 30), /* WKUP_EVT */ > > +}; > > + > > Why cant we set this in the k3-pinctrl.h and set it once? Good idea to define the bit offsets k3-pinctrl.h instead of magic numbers here :) > The event will not be generated until wakeup daisy chain is triggered > anyways. Yup, and having that happen is enough to show the wake-up reason with grep wakeup /proc/interrupts :) > Have you looked at all the padconf registers across devices to ensure > the WKUP_EN/EVT bits are present? daisy chain feature is used elsewhere > as well. The lack of bits at least earlier just meant that attempting to use a wake-up interrupt would just never trigger. Worth checking though. Dhruva, care to check if some padconf register have reserved bits for 29 and 30 that might be set high by default? Regards, Tony
On Aug 07, 2023 at 10:07:24 +0300, Tony Lindgren wrote: > * Nishanth Menon <nm@ti.com> [230805 17:15]: > > On 10:25-20230805, Dhruva Gole wrote: > > > From: Tony Lindgren <tony@atomide.com> > > > +static const struct pcs_soc_data pinctrl_single_am625 = { > > > + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, > > > + .irq_enable_mask = (1 << 29), /* WKUP_EN */ > > > + .irq_status_mask = (1 << 30), /* WKUP_EVT */ > > > +}; > > > + > > > > Why cant we set this in the k3-pinctrl.h and set it once? Do you mean that I set 1 << 29 and 30 as sort of macros in the k3-pinctrl.h file and then include it in pinctrl-single.c? Are we okay to #include a header from arch/arm64/boot/dts/ti? > > Good idea to define the bit offsets k3-pinctrl.h instead of magic numbers > here :) If I understand what Nishanth is saying correctly, are we expected to set the wake_en bit on every single K3 SoC's every single padconf reg? I am a little sceptical with this approach, because what is people _don't_ want to wakeup from certain pads? What would be the right way to disable wakeup on those pads then? > > > The event will not be generated until wakeup daisy chain is triggered > > anyways. Any voltage level shift can potentially trigger a daisychain and I don't think that's really such a good idea? > > Yup, and having that happen is enough to show the wake-up reason with > grep wakeup /proc/interrupts :) > > > Have you looked at all the padconf registers across devices to ensure > > the WKUP_EN/EVT bits are present? daisy chain feature is used elsewhere > > as well. In my limited experience, I have only seen daisychain wakeups being enabled on AM62x SOC. This is because this is one of the first K3 devices to implement deepsleep, and I think IO daisychain only applies for wakeups in the case of deepsleep kind of scenarios. > > The lack of bits at least earlier just meant that attempting to use a > wake-up interrupt would just never trigger. Worth checking though. > Dhruva, care to check if some padconf register have reserved bits for > 29 and 30 that might be set high by default? Sure, I could take a look, but setting wake_en on all pads still doesn't feel right to me. > > Regards, > > Tony To summarise, I don't think any other devices are using daisychain atleast today, and even if there is possibility of using in future I think the same compatible I have used here can be used to set wake_en wherever applicable, for eg. whenever AM62A would want to use daisychain it can use this quirk in it's DT node. I believe that we shouldn't set every pad as daisychain enabled otherwise in deepsleep it may result in unintended wakeups. And the way I thought we can give this choice to the user is using wakeirq chained interrupt along with this quirk, compatible = "ti,am6-padconf";
* Dhruva Gole <d-gole@ti.com> [230807 08:09]: > On Aug 07, 2023 at 10:07:24 +0300, Tony Lindgren wrote: > > * Nishanth Menon <nm@ti.com> [230805 17:15]: > > > On 10:25-20230805, Dhruva Gole wrote: > > > > From: Tony Lindgren <tony@atomide.com> > > > > +static const struct pcs_soc_data pinctrl_single_am625 = { > > > > + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, > > > > + .irq_enable_mask = (1 << 29), /* WKUP_EN */ > > > > + .irq_status_mask = (1 << 30), /* WKUP_EVT */ > > > > +}; > > > > + > > > > > > Why cant we set this in the k3-pinctrl.h and set it once? > > Do you mean that I set 1 << 29 and 30 as sort of macros in the > k3-pinctrl.h file and then include it in pinctrl-single.c? > > Are we okay to #include a header from arch/arm64/boot/dts/ti? Yes, but SoC specific defines needs to start with a SoC specific prefix as multiple files may be included for various SoCs. > If I understand what Nishanth is saying correctly, are we expected to > set the wake_en bit on every single K3 SoC's every single padconf reg? > > I am a little sceptical with this approach, because what is people > _don't_ want to wakeup from certain pads? What would be the right way to > disable wakeup on those pads then? The wake_en only gets set when some driver does request_irq() on the wakeirq. No need to set them all. > Sure, I could take a look, but setting wake_en on all pads still > doesn't feel right to me. No need to set all wake_en pads, just checking that if request_irq() is done for some pin that does not have wake_en capability does not cause eternal interrupts if a reserved bit is high all the time :) Regards, Tony
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index f056923ecc98..3a2a9910f2ec 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1954,6 +1954,12 @@ static const struct pcs_soc_data pinctrl_single_am437x = { .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ }; +static const struct pcs_soc_data pinctrl_single_am625 = { + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, + .irq_enable_mask = (1 << 29), /* WKUP_EN */ + .irq_status_mask = (1 << 30), /* WKUP_EVT */ +}; + static const struct pcs_soc_data pinctrl_single = { }; @@ -1962,6 +1968,7 @@ static const struct pcs_soc_data pinconf_single = { }; static const struct of_device_id pcs_of_match[] = { + { .compatible = "ti,am625-padconf", .data = &pinctrl_single_am625 }, { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },