diff mbox series

[V4,12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi

Message ID 20221111032811.2456916-13-peng.fan@oss.nxp.com
State New
Headers
Series arm64: dts: imx8m-evk: misc dts update |

Commit Message

Peng Fan (OSS) Nov. 11, 2022, 3:28 a.m. UTC 
  From: Sherry Sun <sherry.sun@nxp.com>

Enable usdhc1 which is used for wifi.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27 +++++++++++++
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 +++++++++++++++++++
 2 files changed, 66 insertions(+)

Comments

Marco Felsch Nov. 11, 2022, 9:02 a.m. UTC | #1 
Hi Peng,

On 22-11-11, Peng Fan (OSS) wrote:
> From: Sherry Sun <sherry.sun@nxp.com>
> 
> Enable usdhc1 which is used for wifi.
> 
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27 +++++++++++++
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 +++++++++++++++++++
>  2 files changed, 66 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> index a2b24d4d4e3e..7b80f144327d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> @@ -15,6 +15,13 @@ / {
>  	aliases {
>  		spi0 = &flexspi;
>  	};
> +
> +	usdhc1_pwrseq: usdhc1_pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
> +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> +	};
>  };
>  
>  &ddrc {
> @@ -53,6 +60,19 @@ flash@0 {
>  	};
>  };
>  
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
> +	bus-width = <4>;
> +	keep-power-in-suspend;
> +	mmc-pwrseq = <&usdhc1_pwrseq>;
> +	non-removable;
> +	wakeup-source;
> +	status = "okay";
> +};
> +
>  &usdhc3 {
>  	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
>  	assigned-clock-rates = <400000000>;
> @@ -125,4 +145,11 @@ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
>  			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
>  		>;
>  	};
> +
> +	pinctrl_wlan: wlangrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
> +			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x159
> +		>;
> +	};

Out of curiousity, this is not shareable with the other ddr4 evk?

Regards,
  Marco

>  };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 7d6317d95b13..ce450965e837 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
>  		>;
>  	};
>  
> +	pinctrl_usdhc1_gpio: usdhc1grpgpio {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
> +		>;
> +	};
> +
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
> +		>;
> +	};
> +
>  	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
> -- 
> 2.37.1
> 
> 
>
Peng Fan Nov. 11, 2022, 9:08 a.m. UTC | #2 
Sherry,

> Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> support wifi
> 
> Hi Peng,
> 
> On 22-11-11, Peng Fan (OSS) wrote:
> > From: Sherry Sun <sherry.sun@nxp.com>
> >
> > Enable usdhc1 which is used for wifi.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27 +++++++++++++
> > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39
> +++++++++++++++++++
> >  2 files changed, 66 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > index a2b24d4d4e3e..7b80f144327d 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > @@ -15,6 +15,13 @@ / {
> >  	aliases {
> >  		spi0 = &flexspi;
> >  	};
> > +
> > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > +		compatible = "mmc-pwrseq-simple";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
> > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > +	};
> >  };
> >
> >  &ddrc {
> > @@ -53,6 +60,19 @@ flash@0 {
> >  	};
> >  };
> >
> > +&usdhc1 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
> > +	bus-width = <4>;
> > +	keep-power-in-suspend;
> > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > +	non-removable;
> > +	wakeup-source;
> > +	status = "okay";
> > +};
> > +
> >  &usdhc3 {
> >  	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> >  	assigned-clock-rates = <400000000>;
> > @@ -125,4 +145,11 @@ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 0x1d6
> >  			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 0x196
> >  		>;
> >  	};
> > +
> > +	pinctrl_wlan: wlangrp {
> > +		fsl,pins = <
> > +
> 	MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> 	0x141
> > +			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9
> 	0x159
> > +		>;
> > +	};
> 
> Out of curiousity, this is not shareable with the other ddr4 evk?
[Peng Fan] 

Could you please help answer?

Thanks,
Peng.

> 
> Regards,
>   Marco
> 
> >  };
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > index 7d6317d95b13..ce450965e837 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX
> 	0x140
> >  		>;
> >  	};
> >
> > +	pinctrl_usdhc1_gpio: usdhc1grpgpio {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1: usdhc1grp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x190
> > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d0
> > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 	0x1d0
> > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 	0x1d0
> > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 	0x1d0
> > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 	0x1d0
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x194
> > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d4
> > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 	0x1d4
> > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 	0x1d4
> > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 	0x1d4
> > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 	0x1d4
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> 	0x196
> > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> 	0x1d6
> > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 	0x1d6
> > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 	0x1d6
> > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 	0x1d6
> > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 	0x1d6
> > +		>;
> > +	};
> > +
> >  	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
> >  		fsl,pins = <
> >  			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15
> 	0x1c4
> > --
> > 2.37.1
> >
> >
> >
Sherry Sun Nov. 11, 2022, 9:18 a.m. UTC | #3 
> -----Original Message-----
> From: Peng Fan <peng.fan@nxp.com>
> Sent: 2022年11月11日 17:08
> To: Marco Felsch <m.felsch@pengutronix.de>; Peng Fan (OSS)
> <peng.fan@oss.nxp.com>
> Cc: shawnguo@kernel.org; s.hauer@pengutronix.de; linux-
> kernel@vger.kernel.org; Sherry Sun <sherry.sun@nxp.com>;
> kernel@pengutronix.de; festevam@gmail.com; linux-arm-
> kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: RE: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> support wifi
> 
> Sherry,
> 
> > Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> > support wifi
> >
> > Hi Peng,
> >
> > On 22-11-11, Peng Fan (OSS) wrote:
> > > From: Sherry Sun <sherry.sun@nxp.com>
> > >
> > > Enable usdhc1 which is used for wifi.
> > >
> > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27 +++++++++++++
> > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39
> > +++++++++++++++++++
> > >  2 files changed, 66 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > index a2b24d4d4e3e..7b80f144327d 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > @@ -15,6 +15,13 @@ / {
> > >  	aliases {
> > >  		spi0 = &flexspi;
> > >  	};
> > > +
> > > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > > +		compatible = "mmc-pwrseq-simple";
> > > +		pinctrl-names = "default";
> > > +		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
> > > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > > +	};
> > >  };
> > >
> > >  &ddrc {
> > > @@ -53,6 +60,19 @@ flash@0 {
> > >  	};
> > >  };
> > >
> > > +&usdhc1 {
> > > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
> > > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
> > > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
> > > +	bus-width = <4>;
> > > +	keep-power-in-suspend;
> > > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > > +	non-removable;
> > > +	wakeup-source;
> > > +	status = "okay";
> > > +};
> > > +
> > >  &usdhc3 {
> > >  	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> > >  	assigned-clock-rates = <400000000>; @@ -125,4 +145,11 @@
> > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> > 0x1d6
> > >  			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > 0x196
> > >  		>;
> > >  	};
> > > +
> > > +	pinctrl_wlan: wlangrp {
> > > +		fsl,pins = <
> > > +
> > 	MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> > 	0x141
> > > +			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9
> > 	0x159
> > > +		>;
> > > +	};
> >
> > Out of curiousity, this is not shareable with the other ddr4 evk?
> [Peng Fan]
> 
> Could you please help answer?
> 

Hi Peng, I suggest to remove the pinctrl_wlan configure here, it should be added along with the wifi wowlan subnode later.

Best Regards
Sherry


> Thanks,
> Peng.
> 
> >
> > Regards,
> >   Marco
> >
> > >  };
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > index 7d6317d95b13..ce450965e837 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX
> > 	0x140
> > >  		>;
> > >  	};
> > >
> > > +	pinctrl_usdhc1_gpio: usdhc1grpgpio {
> > > +		fsl,pins = <
> > > +			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
> > > +		>;
> > > +	};
> > > +
> > > +	pinctrl_usdhc1: usdhc1grp {
> > > +		fsl,pins = <
> > > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> > 	0x190
> > > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> > 	0x1d0
> > > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > 	0x1d0
> > > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > 	0x1d0
> > > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > 	0x1d0
> > > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > 	0x1d0
> > > +		>;
> > > +	};
> > > +
> > > +	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> > > +		fsl,pins = <
> > > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> > 	0x194
> > > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> > 	0x1d4
> > > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > 	0x1d4
> > > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > 	0x1d4
> > > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > 	0x1d4
> > > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > 	0x1d4
> > > +		>;
> > > +	};
> > > +
> > > +	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> > > +		fsl,pins = <
> > > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> > 	0x196
> > > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> > 	0x1d6
> > > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > 	0x1d6
> > > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > 	0x1d6
> > > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > 	0x1d6
> > > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > 	0x1d6
> > > +		>;
> > > +	};
> > > +
> > >  	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
> > >  		fsl,pins = <
> > >  			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15
> > 	0x1c4
> > > --
> > > 2.37.1
> > >
> > >
> > >
Marco Felsch Nov. 11, 2022, 9:30 a.m. UTC | #4 
On 22-11-11, Sherry Sun wrote:
> 
> 
> > -----Original Message-----
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: 2022年11月11日 17:08
> > To: Marco Felsch <m.felsch@pengutronix.de>; Peng Fan (OSS)
> > <peng.fan@oss.nxp.com>
> > Cc: shawnguo@kernel.org; s.hauer@pengutronix.de; linux-
> > kernel@vger.kernel.org; Sherry Sun <sherry.sun@nxp.com>;
> > kernel@pengutronix.de; festevam@gmail.com; linux-arm-
> > kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> > Subject: RE: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> > support wifi
> > 
> > Sherry,
> > 
> > > Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> > > support wifi
> > >
> > > Hi Peng,
> > >
> > > On 22-11-11, Peng Fan (OSS) wrote:
> > > > From: Sherry Sun <sherry.sun@nxp.com>
> > > >
> > > > Enable usdhc1 which is used for wifi.
> > > >
> > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > >  arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27 +++++++++++++
> > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39
> > > +++++++++++++++++++
> > > >  2 files changed, 66 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > index a2b24d4d4e3e..7b80f144327d 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > @@ -15,6 +15,13 @@ / {
> > > >  	aliases {
> > > >  		spi0 = &flexspi;
> > > >  	};
> > > > +
> > > > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > > > +		compatible = "mmc-pwrseq-simple";
> > > > +		pinctrl-names = "default";
> > > > +		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
> > > > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > > > +	};
> > > >  };
> > > >
> > > >  &ddrc {
> > > > @@ -53,6 +60,19 @@ flash@0 {
> > > >  	};
> > > >  };
> > > >
> > > > +&usdhc1 {
> > > > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
> > > > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
> > > > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
> > > > +	bus-width = <4>;
> > > > +	keep-power-in-suspend;
> > > > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > > > +	non-removable;
> > > > +	wakeup-source;
> > > > +	status = "okay";
> > > > +};
> > > > +
> > > >  &usdhc3 {
> > > >  	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> > > >  	assigned-clock-rates = <400000000>; @@ -125,4 +145,11 @@
> > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> > > 0x1d6
> > > >  			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > > 0x196
> > > >  		>;
> > > >  	};
> > > > +
> > > > +	pinctrl_wlan: wlangrp {
> > > > +		fsl,pins = <
> > > > +
> > > 	MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> > > 	0x141
> > > > +			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9
> > > 	0x159
> > > > +		>;
> > > > +	};
> > >
> > > Out of curiousity, this is not shareable with the other ddr4 evk?
> > [Peng Fan]
> > 
> > Could you please help answer?
> > 
> 
> Hi Peng, I suggest to remove the pinctrl_wlan configure here, it should be added along with the wifi wowlan subnode later.

Does this apply to the imx8mn-evk patch as well?

Also if the usdhc1 is used only for WLAN and this patch series don't add
the WLAN subnode, we could remove this patch and the imx8mn-evk usdhc1
patch completely till you have a complete patchset adding the full WLAN
support.

Regards,
  Marco

> 
> Best Regards
> Sherry
> 
> 
> > Thanks,
> > Peng.
> > 
> > >
> > > Regards,
> > >   Marco
> > >
> > > >  };
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > index 7d6317d95b13..ce450965e837 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX
> > > 	0x140
> > > >  		>;
> > > >  	};
> > > >
> > > > +	pinctrl_usdhc1_gpio: usdhc1grpgpio {
> > > > +		fsl,pins = <
> > > > +			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
> > > > +		>;
> > > > +	};
> > > > +
> > > > +	pinctrl_usdhc1: usdhc1grp {
> > > > +		fsl,pins = <
> > > > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> > > 	0x190
> > > > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> > > 	0x1d0
> > > > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > > 	0x1d0
> > > > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > > 	0x1d0
> > > > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > > 	0x1d0
> > > > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > > 	0x1d0
> > > > +		>;
> > > > +	};
> > > > +
> > > > +	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> > > > +		fsl,pins = <
> > > > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> > > 	0x194
> > > > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> > > 	0x1d4
> > > > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > > 	0x1d4
> > > > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > > 	0x1d4
> > > > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > > 	0x1d4
> > > > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > > 	0x1d4
> > > > +		>;
> > > > +	};
> > > > +
> > > > +	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> > > > +		fsl,pins = <
> > > > +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
> > > 	0x196
> > > > +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
> > > 	0x1d6
> > > > +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > > 	0x1d6
> > > > +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > > 	0x1d6
> > > > +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > > 	0x1d6
> > > > +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > > 	0x1d6
> > > > +		>;
> > > > +	};
> > > > +
> > > >  	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
> > > >  		fsl,pins = <
> > > >  			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15
> > > 	0x1c4
> > > > --
> > > > 2.37.1
> > > >
> > > >
> > > >
Sherry Sun Nov. 11, 2022, 11:31 a.m. UTC | #5 
> -----Original Message-----
> From: Marco Felsch <m.felsch@pengutronix.de>
> Sent: 2022年11月11日 17:30
> To: Sherry Sun <sherry.sun@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>; Peng Fan (OSS)
> <peng.fan@oss.nxp.com>; shawnguo@kernel.org; s.hauer@pengutronix.de;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; festevam@gmail.com;
> linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> support wifi
> 
> On 22-11-11, Sherry Sun wrote:
> >
> >
> > > -----Original Message-----
> > > From: Peng Fan <peng.fan@nxp.com>
> > > Sent: 2022年11月11日 17:08
> > > To: Marco Felsch <m.felsch@pengutronix.de>; Peng Fan (OSS)
> > > <peng.fan@oss.nxp.com>
> > > Cc: shawnguo@kernel.org; s.hauer@pengutronix.de; linux-
> > > kernel@vger.kernel.org; Sherry Sun <sherry.sun@nxp.com>;
> > > kernel@pengutronix.de; festevam@gmail.com; linux-arm-
> > > kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> > > Subject: RE: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1
> > > to support wifi
> > >
> > > Sherry,
> > >
> > > > Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable
> > > > usdhc1 to support wifi
> > > >
> > > > Hi Peng,
> > > >
> > > > On 22-11-11, Peng Fan (OSS) wrote:
> > > > > From: Sherry Sun <sherry.sun@nxp.com>
> > > > >
> > > > > Enable usdhc1 which is used for wifi.
> > > > >
> > > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > >  arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27
> > > > > +++++++++++++ arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |
> 39
> > > > +++++++++++++++++++
> > > > >  2 files changed, 66 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > index a2b24d4d4e3e..7b80f144327d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > @@ -15,6 +15,13 @@ / {
> > > > >  	aliases {
> > > > >  		spi0 = &flexspi;
> > > > >  	};
> > > > > +
> > > > > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > > > > +		compatible = "mmc-pwrseq-simple";
> > > > > +		pinctrl-names = "default";
> > > > > +		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
> > > > > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > > > > +	};
> > > > >  };
> > > > >
> > > > >  &ddrc {
> > > > > @@ -53,6 +60,19 @@ flash@0 {
> > > > >  	};
> > > > >  };
> > > > >
> > > > > +&usdhc1 {
> > > > > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > > > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
> > > > > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
> > > > > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
> > > > > +	bus-width = <4>;
> > > > > +	keep-power-in-suspend;
> > > > > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > > > > +	non-removable;
> > > > > +	wakeup-source;
> > > > > +	status = "okay";
> > > > > +};
> > > > > +
> > > > >  &usdhc3 {
> > > > >  	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> > > > >  	assigned-clock-rates = <400000000>; @@ -125,4 +145,11 @@
> > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> > > > 0x1d6
> > > > >  			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > > > 0x196
> > > > >  		>;
> > > > >  	};
> > > > > +
> > > > > +	pinctrl_wlan: wlangrp {
> > > > > +		fsl,pins = <
> > > > > +
> > > > 	MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> > > > 	0x141
> > > > > +			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9
> > > > 	0x159
> > > > > +		>;
> > > > > +	};
> > > >
> > > > Out of curiousity, this is not shareable with the other ddr4 evk?
> > > [Peng Fan]
> > >
> > > Could you please help answer?
> > >
> >
> > Hi Peng, I suggest to remove the pinctrl_wlan configure here, it should be
> added along with the wifi wowlan subnode later.
> 
> Does this apply to the imx8mn-evk patch as well?
> 
> Also if the usdhc1 is used only for WLAN and this patch series don't add the
> WLAN subnode, we could remove this patch and the imx8mn-evk usdhc1
> patch completely till you have a complete patchset adding the full WLAN
> support.
> 

Hi Marco, actually here enable usdhc1 can support the wifi basic function, so this patch is ok to enable wifi on 8mm, same for 8mn.
But pinctrl_wlan is used to support the out-of-band WoWLAN feature, needs to be used with wifi child dts node, which looks like the following code.

So I suggest to add the pinctrl_wlan along with the wifi_wake_host child node later to support the wifi WoWLAN function. Here only need to enable the usdhc1 to support wifi basic function, no need to add pinctrl_wlan.

&usdhc1 {
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
    pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
    pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
    pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
    bus-width = <4>;
    keep-power-in-suspend;
    non-removable;
    wakeup-source;
    mmc-pwrseq = <&usdhc1_pwrseq>;
    status = "okay";

    wifi_wake_host {
        compatible = "nxp,wifi-wake-host";
        interrupt-parent = <&gpio2>;
        interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
        interrupt-names = "host-wake";
    };
};

Best Regards
Sherry
Marco Felsch Nov. 11, 2022, 11:48 a.m. UTC | #6 
On 22-11-11, Sherry Sun wrote:
> 
> 
> > -----Original Message-----
> > From: Marco Felsch <m.felsch@pengutronix.de>
> > Sent: 2022年11月11日 17:30
> > To: Sherry Sun <sherry.sun@nxp.com>
> > Cc: Peng Fan <peng.fan@nxp.com>; Peng Fan (OSS)
> > <peng.fan@oss.nxp.com>; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > linux-kernel@vger.kernel.org; kernel@pengutronix.de; festevam@gmail.com;
> > linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> > Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to
> > support wifi
> > 
> > On 22-11-11, Sherry Sun wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Peng Fan <peng.fan@nxp.com>
> > > > Sent: 2022年11月11日 17:08
> > > > To: Marco Felsch <m.felsch@pengutronix.de>; Peng Fan (OSS)
> > > > <peng.fan@oss.nxp.com>
> > > > Cc: shawnguo@kernel.org; s.hauer@pengutronix.de; linux-
> > > > kernel@vger.kernel.org; Sherry Sun <sherry.sun@nxp.com>;
> > > > kernel@pengutronix.de; festevam@gmail.com; linux-arm-
> > > > kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>
> > > > Subject: RE: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1
> > > > to support wifi
> > > >
> > > > Sherry,
> > > >
> > > > > Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable
> > > > > usdhc1 to support wifi
> > > > >
> > > > > Hi Peng,
> > > > >
> > > > > On 22-11-11, Peng Fan (OSS) wrote:
> > > > > > From: Sherry Sun <sherry.sun@nxp.com>
> > > > > >
> > > > > > Enable usdhc1 which is used for wifi.
> > > > > >
> > > > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > ---
> > > > > >  arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 27
> > > > > > +++++++++++++ arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |
> > 39
> > > > > +++++++++++++++++++
> > > > > >  2 files changed, 66 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > > index a2b24d4d4e3e..7b80f144327d 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > > > > > @@ -15,6 +15,13 @@ / {
> > > > > >  	aliases {
> > > > > >  		spi0 = &flexspi;
> > > > > >  	};
> > > > > > +
> > > > > > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > > > > > +		compatible = "mmc-pwrseq-simple";
> > > > > > +		pinctrl-names = "default";
> > > > > > +		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
> > > > > > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > > > > > +	};
> > > > > >  };
> > > > > >
> > > > > >  &ddrc {
> > > > > > @@ -53,6 +60,19 @@ flash@0 {
> > > > > >  	};
> > > > > >  };
> > > > > >
> > > > > > +&usdhc1 {
> > > > > > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > > > > +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
> > > > > > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
> > > > > > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
> > > > > > +	bus-width = <4>;
> > > > > > +	keep-power-in-suspend;
> > > > > > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > > > > > +	non-removable;
> > > > > > +	wakeup-source;
> > > > > > +	status = "okay";
> > > > > > +};
> > > > > > +
> > > > > >  &usdhc3 {
> > > > > >  	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> > > > > >  	assigned-clock-rates = <400000000>; @@ -125,4 +145,11 @@
> > > > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> > > > > 0x1d6
> > > > > >  			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > > > > 0x196
> > > > > >  		>;
> > > > > >  	};
> > > > > > +
> > > > > > +	pinctrl_wlan: wlangrp {
> > > > > > +		fsl,pins = <
> > > > > > +
> > > > > 	MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> > > > > 	0x141
> > > > > > +			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9
> > > > > 	0x159
> > > > > > +		>;
> > > > > > +	};
> > > > >
> > > > > Out of curiousity, this is not shareable with the other ddr4 evk?
> > > > [Peng Fan]
> > > >
> > > > Could you please help answer?
> > > >
> > >
> > > Hi Peng, I suggest to remove the pinctrl_wlan configure here, it should be
> > added along with the wifi wowlan subnode later.
> > 
> > Does this apply to the imx8mn-evk patch as well?
> > 
> > Also if the usdhc1 is used only for WLAN and this patch series don't add the
> > WLAN subnode, we could remove this patch and the imx8mn-evk usdhc1
> > patch completely till you have a complete patchset adding the full WLAN
> > support.
> > 
> 
> Hi Marco, actually here enable usdhc1 can support the wifi basic
> function, so this patch is ok to enable wifi on 8mm, same for 8mn.

Okay, thanks for the clarification.

> But pinctrl_wlan is used to support the out-of-band WoWLAN feature,
> needs to be used with wifi child dts node, which looks like the
> following code.
> 
> So I suggest to add the pinctrl_wlan along with the wifi_wake_host
> child node later to support the wifi WoWLAN function. Here only need
> to enable the usdhc1 to support wifi basic function, no need to add
> pinctrl_wlan.

+1 from my side. @Peng can you drop the pinctrl_wlan from this patch and
from the mx8mn patch as well?

Regards,
  Marco

> &usdhc1 {
>     pinctrl-names = "default", "state_100mhz", "state_200mhz";
>     pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
>     pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
>     pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
>     bus-width = <4>;
>     keep-power-in-suspend;
>     non-removable;
>     wakeup-source;
>     mmc-pwrseq = <&usdhc1_pwrseq>;
>     status = "okay";
> 
>     wifi_wake_host {
>         compatible = "nxp,wifi-wake-host";
>         interrupt-parent = <&gpio2>;
>         interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
>         interrupt-names = "host-wake";
>     };
> };
> 
> Best Regards
> Sherry
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index a2b24d4d4e3e..7b80f144327d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -15,6 +15,13 @@  / {
 	aliases {
 		spi0 = &flexspi;
 	};
+
+	usdhc1_pwrseq: usdhc1_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &ddrc {
@@ -53,6 +60,19 @@  flash@0 {
 	};
 };
 
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
+	bus-width = <4>;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&usdhc1_pwrseq>;
+	non-removable;
+	wakeup-source;
+	status = "okay";
+};
+
 &usdhc3 {
 	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
 	assigned-clock-rates = <400000000>;
@@ -125,4 +145,11 @@  MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 		>;
 	};
+
+	pinctrl_wlan: wlangrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
+			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x159
+		>;
+	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 7d6317d95b13..ce450965e837 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -559,6 +559,45 @@  MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
 		>;
 	};
 
+	pinctrl_usdhc1_gpio: usdhc1grpgpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
+		>;
+	};
+
 	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4