arm64: dts: imx8mp-beacon: Configure 100MHz PCIe Ref Clk
Commit Message
There is a I2C controlled 100MHz Reference clock used by the PCIe
controller. Configure this clock's DIF1 output to be used by
the PCIe.
Signed-off-by: Adam Ford <aford173@gmail.com>
Comments
Hi Adam,
On Sun, Aug 6, 2023 at 4:06 PM Adam Ford <aford173@gmail.com> wrote:
> &pcie_phy {
> + fsl,clkreq-unsupported;
> fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> - clocks = <&pcie0_refclk>;
Should the pcie0_refclk node be also removed? It seems to be unused
after this patch.
> + clocks = <&pcieclk 1>;
Isn't clocks = <&pcieclk>; (without the extra 1) enough?
On Sun, Aug 6, 2023 at 5:03 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Adam,
>
> On Sun, Aug 6, 2023 at 4:06 PM Adam Ford <aford173@gmail.com> wrote:
>
> > &pcie_phy {
> > + fsl,clkreq-unsupported;
> > fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > - clocks = <&pcie0_refclk>;
>
> Should the pcie0_refclk node be also removed? It seems to be unused
> after this patch.
Oops, you're right. I will send a V2.
>
> > + clocks = <&pcieclk 1>;
>
> Isn't clocks = <&pcieclk>; (without the extra 1) enough?
The clock generator has two outputs called DIF0 and DIF1. This
hardware uses DIF1 for the reference clock, so I need to specify
output 1.
adam
@@ -23,6 +23,12 @@ chosen {
stdout-path = &uart2;
};
+ clk_xtal25: clk-xtal25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
@@ -246,6 +252,13 @@ pca6416_3: gpio@20 {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ pcieclk: clk@68 {
+ compatible = "renesas,9fgv0241";
+ reg = <0x68>;
+ clocks = <&clk_xtal25>;
+ #clock-cells = <1>;
+ };
};
&i2c3 {
@@ -372,8 +385,9 @@ &pcie {
};
&pcie_phy {
+ fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- clocks = <&pcie0_refclk>;
+ clocks = <&pcieclk 1>;
clock-names = "ref";
status = "okay";
};