Message ID | 20230803111017.2418-1-xiaoyong.lu@mediatek.com |
---|---|
State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ay21-20020a170906d29500b00988357b5f3fsi2942155ejb.758.2023.08.03.05.40.11; Thu, 03 Aug 2023 05:40:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PiwlT4zT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231449AbjHCLLf (ORCPT <rfc822;jeff.pang.chn@gmail.com> + 99 others); Thu, 3 Aug 2023 07:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229446AbjHCLLP (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 3 Aug 2023 07:11:15 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9232E3C34; Thu, 3 Aug 2023 04:10:25 -0700 (PDT) X-UUID: 56366f4e31ee11ee9cb5633481061a41-20230803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=y1/bPs/BxFNXGqv9H1rzERGNtX0OyJ3swYdBbl4atw8=; b=PiwlT4zTQLrBxUTvpO2LqKe3RXbRHrZI5s7jRxkt1Li47C31rASohhHiZ09f8cmFkVQR6Fuq6nimT9R6CgSYGWBLH/m0wH1pkYHLlny1CqPH4dheqMiuw2NwuQiG+oK6Imx+fRN7KtdcrReOXdWjGr5ImyVE2K6V60t1zO9B47k=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.30,REQID:3ca707d5-4d6d-44b1-9403-71d81f6d01a6,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:1fcc6f8,CLOUDID:99a6d9a0-0933-4333-8d4f-6c3c53ebd55b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 56366f4e31ee11ee9cb5633481061a41-20230803 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from <xiaoyong.lu@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1716315439; Thu, 03 Aug 2023 19:10:21 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 3 Aug 2023 19:10:19 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 3 Aug 2023 19:10:18 +0800 From: Xiaoyong Lu <xiaoyong.lu@mediatek.com> To: Yunfei Dong <yunfei.dong@mediatek.com>, Alexandre Courbot <acourbot@chromium.org>, Nicolas Dufresne <nicolas@ndufresne.ca>, "Hans Verkuil" <hverkuil-cisco@xs4all.nl>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Benjamin Gaignard <benjamin.gaignard@collabora.com>, Tiffany Lin <tiffany.lin@mediatek.com>, Andrew-CT Chen <andrew-ct.chen@mediatek.com>, Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Tomasz Figa <tfiga@google.com> CC: George Sun <george.sun@mediatek.com>, Xiaoyong Lu <xiaoyong.lu@mediatek.com>, Hsin-Yi Wang <hsinyi@chromium.org>, Fritz Koenig <frkoenig@chromium.org>, Daniel Vetter <daniel@ffwll.ch>, dri-devel <dri-devel@lists.freedesktop.org>, Irui Wang <irui.wang@mediatek.com>, "Steve Cho" <stevecho@chromium.org>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com> Subject: [v3] media: mediatek: vcodec: fix AV1 decoding on MT8188 Date: Thu, 3 Aug 2023 19:10:17 +0800 Message-ID: <20230803111017.2418-1-xiaoyong.lu@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HK_RANDOM_ENVFROM, HK_RANDOM_FROM,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS, T_SCC_BODY_TEXT_LINE,T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773211678806462759 X-GMAIL-MSGID: 1773211678806462759 |
Series |
[v3] media: mediatek: vcodec: fix AV1 decoding on MT8188
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Commit Message
Xiaoyong Lu
Aug. 3, 2023, 11:10 a.m. UTC
Fix AV1 decoding failure when the iova is 36bit.
Before this fix, the decoder was accessing incorrect addresses with 36bit
iova tile buffer, leading to iommu faults.
Fixes: 2f5d0aef37c6 ("media: mediatek: vcodec: support stateless AV1 decoder")
Signed-off-by: Xiaoyong Lu<xiaoyong.lu@mediatek.com>
---
Changes from v2:
- refine commit subject and message
Changes from v1:
- prefer '|' rather than '+'
- prefer '&' rather than shift operation
- add comments for address operations
v1:
- VDEC HW can access tile buffer and decode normally.
- Test ok by mt8195 32bit and mt8188 36bit iova.
---
.../mediatek/vcodec/vdec/vdec_av1_req_lat_if.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
Comments
Hi Xiaoyong, On 8/3/23 14:10, Xiaoyong Lu wrote: > Fix AV1 decoding failure when the iova is 36bit. > > Before this fix, the decoder was accessing incorrect addresses with 36bit > iova tile buffer, leading to iommu faults. > > Fixes: 2f5d0aef37c6 ("media: mediatek: vcodec: support stateless AV1 decoder") > Signed-off-by: Xiaoyong Lu<xiaoyong.lu@mediatek.com> > --- > Changes from v2: > > - refine commit subject and message > > Changes from v1: > > - prefer '|' rather than '+' > - prefer '&' rather than shift operation > - add comments for address operations > > v1: > - VDEC HW can access tile buffer and decode normally. > - Test ok by mt8195 32bit and mt8188 36bit iova. > > --- > .../mediatek/vcodec/vdec/vdec_av1_req_lat_if.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > index 404a1a23fd402..e9f2393f6a883 100644 > --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > @@ -1658,9 +1658,9 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins > u32 allow_update_cdf = 0; > u32 sb_boundary_x_m1 = 0, sb_boundary_y_m1 = 0; > int tile_info_base; > - u32 tile_buf_pa; > + u64 tile_buf_pa; > u32 *tile_info_buf = instance->tile.va; > - u32 pa = (u32)bs->dma_addr; > + u64 pa = (u64)bs->dma_addr; If it this is a dma address, can't we use dma_addr_t ? isn't it more generic? Or maybe you have a specific reason not to ? > > if (uh->disable_cdf_update == 0) > allow_update_cdf = 1; > @@ -1673,8 +1673,12 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins > tile_info_buf[tile_info_base + 0] = (tile_group->tile_size[tile_num] << 3); > tile_buf_pa = pa + tile_group->tile_start_offset[tile_num]; > > - tile_info_buf[tile_info_base + 1] = (tile_buf_pa >> 4) << 4; > - tile_info_buf[tile_info_base + 2] = (tile_buf_pa % 16) << 3; > + /* save av1 tile high 4bits(bit 32-35) address in lower 4 bits position > + * and clear original for hw requirement. > + */ > + tile_info_buf[tile_info_base + 1] = (tile_buf_pa & 0xFFFFFFF0ull) | > + ((tile_buf_pa & 0xF00000000ull) >> 32); > + tile_info_buf[tile_info_base + 2] = (tile_buf_pa & 0xFull) << 3; Would it be better to use GENMASK if you plan to mask out some of the bits in the tile_buf_pa ? > > sb_boundary_x_m1 = > (tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) & Greetings, Eugen
FYI: the v2 patch has already been merged, so I dropped this v3. On 03/08/2023 13:10, Xiaoyong Lu wrote: > Fix AV1 decoding failure when the iova is 36bit. > > Before this fix, the decoder was accessing incorrect addresses with 36bit > iova tile buffer, leading to iommu faults. > > Fixes: 2f5d0aef37c6 ("media: mediatek: vcodec: support stateless AV1 decoder") > Signed-off-by: Xiaoyong Lu<xiaoyong.lu@mediatek.com> > --- > Changes from v2: > > - refine commit subject and message It's only subject/commit message changes, the actual code is the same. Regards, Hans > > Changes from v1: > > - prefer '|' rather than '+' > - prefer '&' rather than shift operation > - add comments for address operations > > v1: > - VDEC HW can access tile buffer and decode normally. > - Test ok by mt8195 32bit and mt8188 36bit iova. > > --- > .../mediatek/vcodec/vdec/vdec_av1_req_lat_if.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > index 404a1a23fd402..e9f2393f6a883 100644 > --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > @@ -1658,9 +1658,9 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins > u32 allow_update_cdf = 0; > u32 sb_boundary_x_m1 = 0, sb_boundary_y_m1 = 0; > int tile_info_base; > - u32 tile_buf_pa; > + u64 tile_buf_pa; > u32 *tile_info_buf = instance->tile.va; > - u32 pa = (u32)bs->dma_addr; > + u64 pa = (u64)bs->dma_addr; > > if (uh->disable_cdf_update == 0) > allow_update_cdf = 1; > @@ -1673,8 +1673,12 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins > tile_info_buf[tile_info_base + 0] = (tile_group->tile_size[tile_num] << 3); > tile_buf_pa = pa + tile_group->tile_start_offset[tile_num]; > > - tile_info_buf[tile_info_base + 1] = (tile_buf_pa >> 4) << 4; > - tile_info_buf[tile_info_base + 2] = (tile_buf_pa % 16) << 3; > + /* save av1 tile high 4bits(bit 32-35) address in lower 4 bits position > + * and clear original for hw requirement. > + */ > + tile_info_buf[tile_info_base + 1] = (tile_buf_pa & 0xFFFFFFF0ull) | > + ((tile_buf_pa & 0xF00000000ull) >> 32); > + tile_info_buf[tile_info_base + 2] = (tile_buf_pa & 0xFull) << 3; > > sb_boundary_x_m1 = > (tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) &
diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c index 404a1a23fd402..e9f2393f6a883 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c @@ -1658,9 +1658,9 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins u32 allow_update_cdf = 0; u32 sb_boundary_x_m1 = 0, sb_boundary_y_m1 = 0; int tile_info_base; - u32 tile_buf_pa; + u64 tile_buf_pa; u32 *tile_info_buf = instance->tile.va; - u32 pa = (u32)bs->dma_addr; + u64 pa = (u64)bs->dma_addr; if (uh->disable_cdf_update == 0) allow_update_cdf = 1; @@ -1673,8 +1673,12 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins tile_info_buf[tile_info_base + 0] = (tile_group->tile_size[tile_num] << 3); tile_buf_pa = pa + tile_group->tile_start_offset[tile_num]; - tile_info_buf[tile_info_base + 1] = (tile_buf_pa >> 4) << 4; - tile_info_buf[tile_info_base + 2] = (tile_buf_pa % 16) << 3; + /* save av1 tile high 4bits(bit 32-35) address in lower 4 bits position + * and clear original for hw requirement. + */ + tile_info_buf[tile_info_base + 1] = (tile_buf_pa & 0xFFFFFFF0ull) | + ((tile_buf_pa & 0xF00000000ull) >> 32); + tile_info_buf[tile_info_base + 2] = (tile_buf_pa & 0xFull) << 3; sb_boundary_x_m1 = (tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) &