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From: Jan Beulich via Gcc-patches <gcc-patches@gcc.gnu.org>
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|
| Series |
x86: (mainly) "prefix_extra" adjustments
|
|
Checks
| Context | Check | Description |
|---|---|---|
| snail/gcc-patch-check | success | Github commit url |
Commit Message
Jan Beulich
Aug. 3, 2023, 8:11 a.m. UTC
In the three remaining instances separate "prefix_0f" and "prefix_rep" are what is wanted instead. gcc/ * config/i386/i386.md (rd<fsgs>base<mode>): Add "prefix_0f" and "prefix_rep". Drop "prefix_extra". (wr<fsgs>base<mode>): Likewise. (ptwrite<mode>): Likewise.
Comments
On Thu, Aug 3, 2023 at 4:11 PM Jan Beulich via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > In the three remaining instances separate "prefix_0f" and "prefix_rep" > are what is wanted instead. Ok. > > gcc/ > > * config/i386/i386.md (rd<fsgs>base<mode>): Add "prefix_0f" and > "prefix_rep". Drop "prefix_extra". > (wr<fsgs>base<mode>): Likewise. > (ptwrite<mode>): Likewise. > > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -25914,7 +25914,8 @@ > "TARGET_64BIT && TARGET_FSGSBASE" > "rd<fsgs>base\t%0" > [(set_attr "type" "other") > - (set_attr "prefix_extra" "2")]) > + (set_attr "prefix_0f" "1") > + (set_attr "prefix_rep" "1")]) > > (define_insn "wr<fsgs>base<mode>" > [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")] > @@ -25922,7 +25923,8 @@ > "TARGET_64BIT && TARGET_FSGSBASE" > "wr<fsgs>base\t%0" > [(set_attr "type" "other") > - (set_attr "prefix_extra" "2")]) > + (set_attr "prefix_0f" "1") > + (set_attr "prefix_rep" "1")]) > > (define_insn "ptwrite<mode>" > [(unspec_volatile [(match_operand:SWI48 0 "nonimmediate_operand" "rm")] > @@ -25930,7 +25932,8 @@ > "TARGET_PTWRITE" > "ptwrite\t%0" > [(set_attr "type" "other") > - (set_attr "prefix_extra" "2")]) > + (set_attr "prefix_0f" "1") > + (set_attr "prefix_rep" "1")]) > > (define_insn "@rdrand<mode>" > [(set (match_operand:SWI248 0 "register_operand" "=r") >
--- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -25914,7 +25914,8 @@ "TARGET_64BIT && TARGET_FSGSBASE" "rd<fsgs>base\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "2")]) + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1")]) (define_insn "wr<fsgs>base<mode>" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")] @@ -25922,7 +25923,8 @@ "TARGET_64BIT && TARGET_FSGSBASE" "wr<fsgs>base\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "2")]) + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1")]) (define_insn "ptwrite<mode>" [(unspec_volatile [(match_operand:SWI48 0 "nonimmediate_operand" "rm")] @@ -25930,7 +25932,8 @@ "TARGET_PTWRITE" "ptwrite\t%0" [(set_attr "type" "other") - (set_attr "prefix_extra" "2")]) + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1")]) (define_insn "@rdrand<mode>" [(set (match_operand:SWI248 0 "register_operand" "=r")