diff mbox series

[v3,2/8] arm64: dts: ti: k3-am62-main: Add node for DSS

Message ID 20230728173438.12995-3-a-bhatia1@ti.com
State New
Headers
Series arm64: ti: k3-am62: Add display support |

Commit Message

Aradhya Bhatia July 28, 2023, 5:34 p.m. UTC 
  Add Display SubSystem (DSS) DT node for the AM625 SoC.

The DSS supports one each of video pipeline (vid) and video-lite
pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and
DPI signals on another (VP2). The video ports are connected to the
pipelines via 2 identical overlay managers (ovr1 and ovr2).

Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Francesco Dolcini Aug. 3, 2023, 2:14 p.m. UTC | #1 
Hello Aradhya, Nishanth and Vignesh

On Fri, Jul 28, 2023 at 11:04:32PM +0530, Aradhya Bhatia wrote:
> Add Display SubSystem (DSS) DT node for the AM625 SoC.
> 
> The DSS supports one each of video pipeline (vid) and video-lite
> pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and
> DPI signals on another (VP2). The video ports are connected to the
> pipelines via 2 identical overlay managers (ovr1 and ovr2).

Not sure on the plan on the whole series, but from my point of view it
would make sense to have (at least) this patch, if deemed correctly,
applied for v6.6.

This will enable others TI AM625 user to start upstreaming their changes
and testing it.

Francesco
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 33b6aadc9083..687b4b4e7f33 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -717,6 +717,29 @@  cpts@3d000 {
 		};
 	};
 
+	dss: dss@30200000 {
+		compatible = "ti,am625-dss";
+		reg = <0x00 0x30200000 0x00 0x1000>, /* common */
+		      <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
+		      <0x00 0x30206000 0x00 0x1000>, /* vid */
+		      <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
+		      <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
+		      <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
+		      <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
+		reg-names = "common", "vidl1", "vid",
+			"ovr1", "ovr2", "vp1", "vp2";
+		power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 186 6>,
+			 <&k3_clks 186 0>,
+			 <&k3_clks 186 2>;
+		clock-names = "fck", "vp1", "vp2";
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		dss_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
 	hwspinlock: spinlock@2a000000 {
 		compatible = "ti,am64-hwspinlock";
 		reg = <0x00 0x2a000000 0x00 0x1000>;