Message ID | 1690948281-2143-3-git-send-email-quic_krichai@quicinc.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp216553vqx; Tue, 1 Aug 2023 22:14:42 -0700 (PDT) X-Google-Smtp-Source: APBJJlEjkmZMnVCsg9zF03uKE94cD5N33J7b8dsOXnRmriIT3nhBf+G6wenJ5nY77jNuQaBvuLCe X-Received: by 2002:a17:90a:65c5:b0:268:6f22:92dd with SMTP id i5-20020a17090a65c500b002686f2292ddmr11816423pjs.14.1690953281973; Tue, 01 Aug 2023 22:14:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690953281; cv=none; d=google.com; s=arc-20160816; b=TsOcATInCQ59zc2H3ftLgLWmTacAJsB5mFAvkGekFCbwPwVQzys9tsXI5FE7JEDhNo cn6o/x/EUOvgNEM9njmgFzT6Ow4TvLdrd0eBYIBnh01j0CvyrwQTHAzwKWNoBqH2ozre 3b+2vPGwLDG5j0d5dKcdTsZBHeLLxu4f4Y6WWTxvHEHooRKrbJEuniArUO12fATbz0Zr 2HwInJ/QLRHYBDLzJissi4lwph2WitIWghizzHa4jgRe9BGt+dYzBDgHKaGEcEdX4Grn zlF7HrM1e3g1T4dKfzL9YYdsefroclfYhLnRCP8+Y9Atm22dbL/OgAKGHaWz+17SB3Gl yOZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=aCTqeYiypmylDmano3NY2XoWN7p0XG0NivnwGEdtRJ8=; fh=n1CFADIM4km2sLF4LPKt1lz1bsJfe5hWSzFV9pGmm8g=; b=TjpQtUSsDZyORXc57Z0I8D4HlFeD6JgaoOBeAtEa/D/lfxoemv0B+P/i//6c58KRJz uYujIVS9XAhnfG+z3wT8Bkd4R337dCqzE0/Rrv4yYJHDTxqpAuKgpPkEcw6V0pZ9prN6 nb+OLgHc+If87+GjMHwJZdKZlRA6cISX/qjFSDQpjAu1aidw0BBYBDws46psOEQQMrK0 r+Y7I1oMTVaJ/ArJ+DlhTidevov57lSjKDxcAYNkVksfKY4ocbFtC7DMqreO+FODS0W7 NAgJyNn0xYljB6EggP3QXWeghoMvlRatIRXraITdWoDZ5+GkSG3py3XYpCgqk48rSD40 kxag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=bIkqMLh5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id na10-20020a17090b4c0a00b0026329075cc5si626619pjb.155.2023.08.01.22.14.28; Tue, 01 Aug 2023 22:14:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=bIkqMLh5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232002AbjHBDvh (ORCPT <rfc822;maxi.paulin@gmail.com> + 99 others); Tue, 1 Aug 2023 23:51:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231370AbjHBDvd (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 1 Aug 2023 23:51:33 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8FD71BF; Tue, 1 Aug 2023 20:51:32 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3723QjFv016384; Wed, 2 Aug 2023 03:51:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=aCTqeYiypmylDmano3NY2XoWN7p0XG0NivnwGEdtRJ8=; b=bIkqMLh5TaSqo0FCVIia1mXAp77WazfgkgpFWQA1CBWza9rY3i99+0x8sbLXzlk3rbmV XlN9jeCmwFhKBuf7/5+HESpPEYw6O+hbvmHHCQCPqBkXoov3+4ZP0n25RqLhKumGvsX8 jz6UCemgh4ozXRvqb5hvtWrA1WNeA6ZUYlhMDgSTKC/JifXcqoczD/vJgKcwz04IsIFR JitQfDGZwb177QkZZwB1Dgi704w7ILp6mnEKnOyxqViS1dK37TK1DSLFpeJeuxMzpH+L 5hAdIcY1/WkYOAbHevz5U9+ZLCdtT2ZHCJ9xScMKD/DZ3fPONw4uRHCHERC+3sn9QTGI Eg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s7bw9gb2w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Aug 2023 03:51:27 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3723pOCX022472; Wed, 2 Aug 2023 03:51:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3s4uukryxe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 02 Aug 2023 03:51:24 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3723pNsg022449; Wed, 2 Aug 2023 03:51:24 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3723pNWd022454; Wed, 02 Aug 2023 03:51:23 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 4587B4B5F; Wed, 2 Aug 2023 09:21:23 +0530 (+0530) From: Krishna chaitanya chundru <quic_krichai@quicinc.com> To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru <quic_krichai@quicinc.com>, Manivannan Sadhasivam <mani@kernel.org>, Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= <kw@linux.com>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com> Subject: [PATCH v5 2/4] PCI: qcom-ep: Add support for D-state change notification Date: Wed, 2 Aug 2023 09:21:19 +0530 Message-Id: <1690948281-2143-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690948281-2143-1-git-send-email-quic_krichai@quicinc.com> References: <1690948281-2143-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rIkpqHjiu7fWwYGocSIukHgdKUwGuyto X-Proofpoint-GUID: rIkpqHjiu7fWwYGocSIukHgdKUwGuyto X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-01_22,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=914 phishscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020033 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773093028210011009 X-GMAIL-MSGID: 1773093028210011009 |
Series |
PCI: endpoint: add D-state change notifier support
|
|
Commit Message
Krishna chaitanya chundru
Aug. 2, 2023, 3:51 a.m. UTC
Add support to pass D-state change notification to Endpoint function driver. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 7 +++++++ 1 file changed, 7 insertions(+)
Comments
Hi Krishna, kernel test robot noticed the following build errors: [auto build test ERROR on pci/next] [also build test ERROR on pci/for-linus linus/master v6.5-rc4 next-20230803] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Krishna-chaitanya-chundru/PCI-endpoint-Add-D-state-change-notifier-support/20230802-115309 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/1690948281-2143-3-git-send-email-quic_krichai%40quicinc.com patch subject: [PATCH v5 2/4] PCI: qcom-ep: Add support for D-state change notification config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20230803/202308031857.u3v2s0bm-lkp@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce: (https://download.01.org/0day-ci/archive/20230803/202308031857.u3v2s0bm-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202308031857.u3v2s0bm-lkp@intel.com/ All errors (new ones prefixed by >>): drivers/pci/controller/dwc/pcie-qcom-ep.c: In function 'qcom_pcie_ep_global_irq_thread': >> drivers/pci/controller/dwc/pcie-qcom-ep.c:597:17: error: implicit declaration of function 'pci_epc_dstate_notify'; did you mean 'pci_epc_bme_notify'? [-Werror=implicit-function-declaration] 597 | pci_epc_dstate_notify(pci->ep.epc, state); | ^~~~~~~~~~~~~~~~~~~~~ | pci_epc_bme_notify cc1: some warnings being treated as errors vim +597 drivers/pci/controller/dwc/pcie-qcom-ep.c 555 556 /* TODO: Notify clients about PCIe state change */ 557 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 558 { 559 struct qcom_pcie_ep *pcie_ep = data; 560 struct dw_pcie *pci = &pcie_ep->pci; 561 struct device *dev = pci->dev; 562 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 563 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); 564 pci_power_t state; 565 u32 dstate, val; 566 567 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 568 status &= mask; 569 570 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 571 dev_dbg(dev, "Received Linkdown event\n"); 572 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 573 pci_epc_linkdown(pci->ep.epc); 574 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 575 dev_dbg(dev, "Received BME event. Link is enabled!\n"); 576 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 577 pci_epc_bme_notify(pci->ep.epc); 578 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 579 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 580 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 581 val |= PARF_PM_CTRL_READY_ENTR_L23; 582 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 583 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 584 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 585 DBI_CON_STATUS_POWER_STATE_MASK; 586 dev_dbg(dev, "Received D%d state event\n", dstate); 587 state = dstate; 588 if (dstate == 3) { 589 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 590 val |= PARF_PM_CTRL_REQ_EXIT_L1; 591 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 592 593 state = PCI_D3hot; 594 if (gpiod_get_value(pcie_ep->reset)) 595 state = PCI_D3cold; 596 } > 597 pci_epc_dstate_notify(pci->ep.epc, state); 598 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 599 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 600 dw_pcie_ep_linkup(&pci->ep); 601 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 602 } else { 603 dev_dbg(dev, "Received unknown event: %d\n", status); 604 } 605 606 return IRQ_HANDLED; 607 } 608
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0fe7f06..22545ff 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -561,6 +561,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) struct device *dev = pci->dev; u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); + pci_power_t state; u32 dstate, val; writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); @@ -583,11 +584,17 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & DBI_CON_STATUS_POWER_STATE_MASK; dev_dbg(dev, "Received D%d state event\n", dstate); + state = dstate; if (dstate == 3) { val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); val |= PARF_PM_CTRL_REQ_EXIT_L1; writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); + + state = PCI_D3hot; + if (gpiod_get_value(pcie_ep->reset)) + state = PCI_D3cold; } + pci_epc_dstate_notify(pci->ep.epc, state); } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); dw_pcie_ep_linkup(&pci->ep);