Message ID | 20230728103042.267646-1-varshini.rajendran@microchip.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fi37-20020a056a0039a500b006826c8d5a31si977743pfb.21.2023.07.28.04.29.18; Fri, 28 Jul 2023 04:29:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=R0kdEcDY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235834AbjG1KeS (ORCPT <rfc822;hanasaki@gmail.com> + 99 others); Fri, 28 Jul 2023 06:34:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236082AbjG1KdK (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 28 Jul 2023 06:33:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62E404EE1 for <linux-kernel@vger.kernel.org>; Fri, 28 Jul 2023 03:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1690540277; x=1722076277; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jCHL+Jd5EMSndMzWvV72eKzuixuestkfs6Y4izjdGGM=; b=R0kdEcDY1HTalcwk3xxdqsh/VZMOiNbKqtpyVgJobL4nRXMoR2vm1ALm yBx8vWalcjLZuWJhThx44xWHMi7g9d7IB9ztxYH1Of/dPQ5KV7mtsddyV 6rl171E05aEjhtjFD/y7RnyZiFujGo6e1nE01NGgsAAOcatI4/PSnR0y3 DTJtvtmPn/rdRNt0xklniq4tdrKCeE6UaDurnyxzdsNvPYD4FzZqbZ9+G aQeGNnJpsmz5G3P/ynWxN2LlCOW7F0F2zDL6CWExkCfSKxTOuap/SIb3U vsI9bCLUg5MkicJzprEu2bF2ZFRXRbMvwpzW9+9hZnx8vRYseXSXAc40q g==; X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="225813947" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jul 2023 03:30:50 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 28 Jul 2023 03:30:50 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 28 Jul 2023 03:30:47 -0700 From: Varshini Rajendran <varshini.rajendran@microchip.com> To: <linux@armlinux.org.uk>, <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <claudiu.beznea@microchip.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> CC: <varshini.rajendran@microchip.com> Subject: [PATCH v3 46/50] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Fri, 28 Jul 2023 16:00:42 +0530 Message-ID: <20230728103042.267646-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772663624877335057 X-GMAIL-MSGID: 1772663624877335057 |
Series |
[v3,01/50] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60, sam9x7 compatible
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Commit Message
Varshini Rajendran
July 28, 2023, 10:30 a.m. UTC
Add config flag for sam9x7 SoC.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
Comments
On 28.07.2023 13:30, Varshini Rajendran wrote: > Add config flag for sam9x7 SoC. > > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> > --- > arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++--- > 1 file changed, 20 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig > index a8c022b4c053..49d38a3a47de 100644 > --- a/arch/arm/mach-at91/Kconfig > +++ b/arch/arm/mach-at91/Kconfig > @@ -141,11 +141,28 @@ config SOC_SAM9X60 > help > Select this if you are using Microchip's SAM9X60 SoC > > +config SOC_SAM9X7 > + bool "SAM9X7" > + depends on ARCH_MULTI_V5 > + select ATMEL_AIC5_IRQ > + select ATMEL_PM if PM > + select ATMEL_SDRAMC > + select CPU_ARM926T > + select HAVE_AT91_USB_CLK > + select HAVE_AT91_GENERATED_CLK > + select HAVE_AT91_SAM9X60_PLL > + select MEMORY > + select PINCTRL_AT91 > + select SOC_SAM_V4_V5 > + select SRAM if PM > + help > + Select this if you are using Microchip's SAM9X7 SoC > + > comment "Clocksource driver selection" > > config ATMEL_CLOCKSOURCE_PIT > bool "Periodic Interval Timer (PIT) support" > - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 > + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 > default SOC_AT91SAM9 || SOC_SAMA5 > select ATMEL_PIT > help > @@ -155,7 +172,7 @@ config ATMEL_CLOCKSOURCE_PIT > > config ATMEL_CLOCKSOURCE_TCB > bool "Timer Counter Blocks (TCB) support" > - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 > + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 > select ATMEL_TCB_CLKSRC > help > Select this to get a high precision clocksource based on a > @@ -166,7 +183,7 @@ config ATMEL_CLOCKSOURCE_TCB > > config MICROCHIP_CLOCKSOURCE_PIT64B > bool "64-bit Periodic Interval Timer (PIT64B) support" > - default SOC_SAM9X60 || SOC_SAMA7 > + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 > select MICROCHIP_PIT64B > help > Select this to get a high resolution clockevent (SAM9X60) or
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a8c022b4c053..49d38a3a47de 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,11 +141,28 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select ATMEL_SDRAMC + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -155,7 +172,7 @@ config ATMEL_CLOCKSOURCE_PIT config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -166,7 +183,7 @@ config ATMEL_CLOCKSOURCE_TCB config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or