Message ID | 20230624131632.2972546-4-bigunclemax@gmail.com |
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State | New |
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([92.51.95.194]) by smtp.gmail.com with ESMTPSA id l1-20020a1ced01000000b003f9b0830107sm5107428wmh.41.2023.06.24.06.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jun 2023 06:17:15 -0700 (PDT) From: Maksim Kiselev <bigunclemax@gmail.com> To: linux-spi@vger.kernel.org Cc: Maksim Kiselev <bigunclemax@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>, Mark Brown <broonie@kernel.org>, Cristian Ciocaltea <cristian.ciocaltea@collabora.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port Date: Sat, 24 Jun 2023 16:16:24 +0300 Message-Id: <20230624131632.2972546-4-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230624131632.2972546-1-bigunclemax@gmail.com> References: <20230624131632.2972546-1-bigunclemax@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769592852752322422?= X-GMAIL-MSGID: =?utf-8?q?1769592852752322422?= |
Series |
Allwinner R329/D1/R528/T113s Dual/Quad SPI modes support
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Commit Message
Maxim Kiselev
June 24, 2023, 1:16 p.m. UTC
Add pinmux node that describes pins on PC port which required for
QSPI mode.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
Comments
Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a): > Add pinmux node that describes pins on PC port which required for > QSPI mode. > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> > --- > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index > 1bb1e5cae602..9f754dd03d85 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { > pins = "PB6", "PB7"; > function = "uart3"; > }; > + > + /omit-if-no-ref/ > + qspi0_pc_pins: qspi0-pc-pins { > + pins = "PC2", "PC3", "PC4", "PC5", "PC6", > + "PC7"; > + function = "spi0"; > + }; Sorry for late review, but it seems I'm missing something. D1 manual says those are pins for ordinary SPI, with HOLD and WP signals. Can they be repurposed for quad SPI? Best regards, Jernej > }; > > ccu: clock-controller@2001000 {
пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <jernej.skrabec@gmail.com>: > > Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a): > > Add pinmux node that describes pins on PC port which required for > > QSPI mode. > > > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> > > --- > > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index > > 1bb1e5cae602..9f754dd03d85 100644 > > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { > > pins = "PB6", "PB7"; > > function = "uart3"; > > }; > > + > > + /omit-if-no-ref/ > > + qspi0_pc_pins: qspi0-pc-pins { > > + pins = "PC2", "PC3", "PC4", "PC5", > "PC6", > > + "PC7"; > > + function = "spi0"; > > + }; > > Sorry for late review, but it seems I'm missing something. D1 manual says > those are pins for ordinary SPI, with HOLD and WP signals. Can they be > repurposed for quad SPI? > Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI Quad-Input/Quad-Output Mode): "Using the quad mode allows data to be transferred to or from the device at 4 times the rate of standard single mode, the data can be read at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 (HOLD#)) at the same time."
Dne ponedeljek, 31. julij 2023 ob 17:22:11 CEST je Maxim Kiselev napisal(a): > пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <jernej.skrabec@gmail.com>: > > Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a): > > > Add pinmux node that describes pins on PC port which required for > > > QSPI mode. > > > > > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> > > > --- > > > > > > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index > > > 1bb1e5cae602..9f754dd03d85 100644 > > > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { > > > > > > pins = "PB6", "PB7"; > > > function = "uart3"; > > > > > > }; > > > > > > + > > > + /omit-if-no-ref/ > > > + qspi0_pc_pins: qspi0-pc-pins { > > > + pins = "PC2", "PC3", "PC4", "PC5", > > > > "PC6", > > > > > + "PC7"; > > > + function = "spi0"; > > > + }; > > > > Sorry for late review, but it seems I'm missing something. D1 manual says > > those are pins for ordinary SPI, with HOLD and WP signals. Can they be > > repurposed for quad SPI? > > Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI > Quad-Input/Quad-Output Mode): > "Using the quad mode allows data to be transferred to or from the > device at 4 times the rate of standard single mode, the data can be > read > at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 > (HOLD#)) at the same time." Alright then. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 1bb1e5cae602..9f754dd03d85 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + qspi0_pc_pins: qspi0-pc-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", + "PC7"; + function = "spi0"; + }; }; ccu: clock-controller@2001000 {