diff mbox series

pwm: tegra: Fix 32 bit build

Message ID 20221110114549.34121-1-steven.price@arm.com
State New
Headers
Series pwm: tegra: Fix 32 bit build |

Commit Message

Steven Price Nov. 10, 2022, 11:45 a.m. UTC 
  The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
integer causing a build warning/error (and the value truncated):

  drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
  drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
    148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
        |                                                     ^~

Explicitly cast to a u64 to ensure the correct result.

Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
Signed-off-by: Steven Price <steven.price@arm.com>
---
 drivers/pwm/pwm-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jon Hunter Nov. 10, 2022, 1:18 p.m. UTC | #1 
On 10/11/2022 11:45, Steven Price wrote:
> The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
> integer causing a build warning/error (and the value truncated):
> 
>    drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
>    drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
>      148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
>          |                                                     ^~
> 
> Explicitly cast to a u64 to ensure the correct result.
> 
> Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
> Signed-off-by: Steven Price <steven.price@arm.com>
> ---
>   drivers/pwm/pwm-tegra.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index 6fc4b69a3ba7..249dc0193297 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -145,7 +145,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>   		 * source clock rate as required_clk_rate, PWM controller will
>   		 * be able to configure the requested period.
>   		 */
> -		required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
> +		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
>   						     period_ns);
>   
>   		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))


Thanks!

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Jon
Uwe Kleine-König Nov. 10, 2022, 2:53 p.m. UTC | #2 
Hello,

On Thu, Nov 10, 2022 at 11:45:48AM +0000, Steven Price wrote:
> The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
> integer causing a build warning/error (and the value truncated):
> 
>   drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
>   drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
>     148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
>         |                                                     ^~
> 
> Explicitly cast to a u64 to ensure the correct result.

Hmm, ideally this should have popped up earlier :-\

Anyhow:

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Thanks
Uwe
Thierry Reding Nov. 11, 2022, 2:30 p.m. UTC | #3 
On Thu, 10 Nov 2022 11:45:48 +0000, Steven Price wrote:
> The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
> integer causing a build warning/error (and the value truncated):
> 
>   drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
>   drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
>     148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
>         |                                                     ^~
> 
> [...]

Applied, thanks!

[1/1] pwm: tegra: Fix 32 bit build
      commit: dd1f1da4ada5d8ac774c2ebe97230637820b3323

Best regards,
diff mbox series

Patch

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 6fc4b69a3ba7..249dc0193297 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -145,7 +145,7 @@  static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 		 * source clock rate as required_clk_rate, PWM controller will
 		 * be able to configure the requested period.
 		 */
-		required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
+		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
 						     period_ns);
 
 		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))