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From: Varshini Rajendran <varshini.rajendran@microchip.com>
To: <tudor.ambarus@linaro.org>, <miquel.raynal@bootlin.com>,
<richard@nod.at>, <vigneshr@ti.com>, <robh+dt@kernel.org>,
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CC: <varshini.rajendran@microchip.com>
Subject: [PATCH v3 20/50] dt-bindings: atmel-nand: add microchip,sam9x7-pmecc
Date: Fri, 28 Jul 2023 15:56:36 +0530
Message-ID: <20230728102636.266309-1-varshini.rajendran@microchip.com>
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[v3,01/50] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60, sam9x7 compatible
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Commit Message
Varshini Rajendran
July 28, 2023, 10:26 a.m. UTC
Add microchip,sam9x7-pmecc to DT bindings documentation.
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
1 file changed, 1 insertion(+)
Comments
On 7/28/23 11:26, Varshini Rajendran wrote: > Add microchip,sam9x7-pmecc to DT bindings documentation. > Why? What's the underlying problem that motivated you do this patch? > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> > --- > Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt > index 50645828ac20..4598930851d9 100644 > --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt > +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt > @@ -56,6 +56,7 @@ Required properties: > "atmel,sama5d4-pmecc" > "atmel,sama5d2-pmecc" > "microchip,sam9x60-pmecc" > + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" > - reg: should contain 2 register ranges. The first one is pointing to the PMECC > block, and the second one to the PMECC_ERRLOC block. >
On 28/07/2023 13:06, Tudor Ambarus wrote: > > > On 7/28/23 11:26, Varshini Rajendran wrote: >> Add microchip,sam9x7-pmecc to DT bindings documentation. >> > > Why? What's the underlying problem that motivated you do this patch? Isn't the problem already described in commit msg, although shortly: There is a new SoC sam9x7, where the model name is sam9x7 and it is not a wild-card nor family name of SoCs, and we add compatible for it, as expected by writing-bindings guideline. Best regards, Krzysztof
On 28/07/23 4:36 pm, Tudor Ambarus wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 7/28/23 11:26, Varshini Rajendran wrote: >> Add microchip,sam9x7-pmecc to DT bindings documentation. >> > > Why? What's the underlying problem that motivated you do this patch? Hi Tudor, The motivation is to have compatibles specific to the SoC. I am aware that there is no change in the IP nor the driver. As Krzysztof mentioned in another patch, this is just to add a SoC specific compatible string. Hope this clears the query. > >> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> >> --- >> Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt >> index 50645828ac20..4598930851d9 100644 >> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt >> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt >> @@ -56,6 +56,7 @@ Required properties: >> "atmel,sama5d4-pmecc" >> "atmel,sama5d2-pmecc" >> "microchip,sam9x60-pmecc" >> + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" >> - reg: should contain 2 register ranges. The first one is pointing to the PMECC >> block, and the second one to the PMECC_ERRLOC block. >> -- Thanks and Regards, Varshini Rajendran.
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index 50645828ac20..4598930851d9 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -56,6 +56,7 @@ Required properties: "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" "microchip,sam9x60-pmecc" + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the PMECC block, and the second one to the PMECC_ERRLOC block.