diff mbox series

arm64/mm: Directly use ID_AA64MMFR2_EL1_VARange_MASK

Message ID 20230711092055.245756-1-anshuman.khandual@arm.com
State New
Headers
Series arm64/mm: Directly use ID_AA64MMFR2_EL1_VARange_MASK |

Commit Message

Anshuman Khandual July 11, 2023, 9:20 a.m. UTC 
  Tools generated register fields have in place mask macros which can be used
directly instead of shifting the older right end sided masks.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
This applies on v6.5-rc1

 arch/arm64/kernel/head.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Will Deacon July 27, 2023, 12:22 p.m. UTC | #1 
On Tue, 11 Jul 2023 14:50:55 +0530, Anshuman Khandual wrote:
> Tools generated register fields have in place mask macros which can be used
> directly instead of shifting the older right end sided masks.
> 
> 

Applied to arm64 (for-next/mm), thanks!

[1/1] arm64/mm: Directly use ID_AA64MMFR2_EL1_VARange_MASK
      https://git.kernel.org/arm64/c/62ce7af97ba5

Cheers,
diff mbox series

Patch

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 757a0de07f91..7b236994f0e1 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -113,7 +113,7 @@  SYM_CODE_START(primary_entry)
 	 */
 #if VA_BITS > 48
 	mrs_s	x0, SYS_ID_AA64MMFR2_EL1
-	tst	x0, #0xf << ID_AA64MMFR2_EL1_VARange_SHIFT
+	tst	x0, ID_AA64MMFR2_EL1_VARange_MASK
 	mov	x0, #VA_BITS
 	mov	x25, #VA_BITS_MIN
 	csel	x25, x25, x0, eq
@@ -756,7 +756,7 @@  SYM_FUNC_START(__cpu_secondary_check52bitva)
 	b.ne	2f
 
 	mrs_s	x0, SYS_ID_AA64MMFR2_EL1
-	and	x0, x0, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)
+	and	x0, x0, ID_AA64MMFR2_EL1_VARange_MASK
 	cbnz	x0, 2f
 
 	update_early_cpu_boot_status \