Message ID | 1690285689-30233-2-git-send-email-quic_vnivarth@quicinc.com |
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State | New |
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Series |
spi: spi-qcom-qspi: Follow-up patches to DMA mode support
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Commit Message
Vijaya Krishna Nivarthi
July 25, 2023, 11:48 a.m. UTC
During FIFO/DMA modes dynamic switching, only corresponding interrupts are
enabled. However its possible that FIFO related interrupt status registers
get set during DMA mode. For example WR_FIFO_EMPTY bit is set during DMA
TX.
Ignore such status bits so that they don't trip unwanted operations.
Suggested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
---
drivers/spi/spi-qcom-qspi.c | 3 +++
1 file changed, 3 insertions(+)
Comments
Hi, On Tue, Jul 25, 2023 at 4:48 AM Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> wrote: > > During FIFO/DMA modes dynamic switching, only corresponding interrupts are > enabled. However its possible that FIFO related interrupt status registers > get set during DMA mode. For example WR_FIFO_EMPTY bit is set during DMA > TX. > > Ignore such status bits so that they don't trip unwanted operations. > > Suggested-by: Douglas Anderson <dianders@chromium.org> > Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> > --- > drivers/spi/spi-qcom-qspi.c | 3 +++ > 1 file changed, 3 insertions(+) Things are pretty broken without this fix, so it definitely needs a Fixes tag so it can find its way to mainline as soon as possible: Fixes: b5762d95607e ("spi: spi-qcom-qspi: Add DMA mode support") Looks good to me and also works fixes the problem for me. Thus I'm happy with any of these tags: Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index a0ad980..b995542 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -603,6 +603,9 @@ static irqreturn_t qcom_qspi_irq(int irq, void *dev_id) int_status = readl(ctrl->base + MSTR_INT_STATUS); writel(int_status, ctrl->base + MSTR_INT_STATUS); + /* Ignore disabled interrupts */ + int_status &= readl(ctrl->base + MSTR_INT_EN); + /* PIO mode handling */ if (ctrl->xfer.dir == QSPI_WRITE) { if (int_status & WR_FIFO_EMPTY)