diff mbox series

[v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations

Message ID 1666590189-1364-1-git-send-email-hongxing.zhu@nxp.com
State New
Headers
Series [v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations |

Commit Message

Richard Zhu Oct. 24, 2022, 5:43 a.m. UTC 
  Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
i.MX8MP PCIe reference clock.

The following properties of PHY dts node should be changed accordingly.
  - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
  - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
Base on 6.1-rc1, and the following PHY changes [1],
the PCIe works fine when SYSPLL is used as reference clock on i.MX8MP
EVK board(schematic-46370) after removing R131/R132/R137/R138, and
populating R135/R136.

[1] https://patchwork.kernel.org/project/linux-pci/cover/1665625622-20551-1-git-send-email-hongxing.zhu@nxp.com/
---
 drivers/soc/imx/imx8mp-blk-ctrl.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Shawn Guo Oct. 29, 2022, 8:45 a.m. UTC | #1 
On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> i.MX8MP PCIe reference clock.
> 
> The following properties of PHY dts node should be changed accordingly.
>   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
>   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Applied, thanks!
Lucas Stach Nov. 1, 2022, 8:44 a.m. UTC | #2 
Hi Shawn, Richard,

Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > i.MX8MP PCIe reference clock.
> > 
> > The following properties of PHY dts node should be changed accordingly.
> >   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> >   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > 
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> 
> Applied, thanks!

Sorry for the late reply, but I'm not really happy with the fact that
the PLL is now unconditionally enabled, even though it is only needed
when there is no external reference clock source.
I fear that this will be hard to correct later on as the DT abstraction
is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
PHY, but the PLL generated clock, which isn't properly exposed with
this series.

I'm not happy to see this going in in the current state and if not too
late would like to ask Shawn to remove it from the tree again.

Regards,
Lucas
Richard Zhu Nov. 2, 2022, 1:45 a.m. UTC | #3 
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年11月1日 16:45
> To: Shawn Guo <shawnguo@kernel.org>; Hongxing Zhu
> <hongxing.zhu@nxp.com>
> Cc: marex@denx.de; tharvey@gateworks.com; vkoul@kernel.org;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com;
> alexander.stein@ew.tq-group.com; richard.leitner@linux.dev;
> devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> configurations
> 
> Hi Shawn, Richard,
> 
> Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used
> > > as i.MX8MP PCIe reference clock.
> > >
> > > The following properties of PHY dts node should be changed accordingly.
> > >   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > >   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Applied, thanks!
> 
> Sorry for the late reply, but I'm not really happy with the fact that the PLL is
> now unconditionally enabled, even though it is only needed when there is no
> external reference clock source.
> I fear that this will be hard to correct later on as the DT abstraction is wrong, as
> IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the PHY, but the PLL
> generated clock, which isn't properly exposed with this series.
Hi Lucas:
First of all, thanks for your comments.

IMHO, I'm not sure it's proper or not to describe the hardware logic in
 the PHY node when internal SYSPLL is used as PCIe PHY reference clock.
So, I'm trying to get some suggestions and used to send out an email to
 you and Marcel on Sep20.

Okay, if you think it's not correct to expose IMX8MP_CLK_HSIO_ROOT clock
 out.
Which clock you are prefer to use as PHY reference clock here?

Thanks.

Best Regards
Richard Zhu
> 
> I'm not happy to see this going in in the current state and if not too late would
> like to ask Shawn to remove it from the tree again.
> 
> Regards,
> Lucas
Shawn Guo Nov. 10, 2022, 7:15 a.m. UTC | #4 
On Tue, Nov 01, 2022 at 09:44:41AM +0100, Lucas Stach wrote:
> Hi Shawn, Richard,
> 
> Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > > i.MX8MP PCIe reference clock.
> > > 
> > > The following properties of PHY dts node should be changed accordingly.
> > >   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > >   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > > 
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > 
> > Applied, thanks!
> 
> Sorry for the late reply, but I'm not really happy with the fact that
> the PLL is now unconditionally enabled, even though it is only needed
> when there is no external reference clock source.
> I fear that this will be hard to correct later on as the DT abstraction
> is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
> PHY, but the PLL generated clock, which isn't properly exposed with
> this series.
> 
> I'm not happy to see this going in in the current state and if not too
> late would like to ask Shawn to remove it from the tree again.

Removed.

Shawn
Richard Zhu Nov. 15, 2022, 2:25 a.m. UTC | #5 
> -----Original Message-----
> From: Hongxing Zhu
> Sent: 2022年11月2日 9:46
> To: Lucas Stach <l.stach@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>
> Cc: marex@denx.de; tharvey@gateworks.com; vkoul@kernel.org;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com;
> alexander.stein@ew.tq-group.com; richard.leitner@linux.dev;
> devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>;
> marcel.ziswiler@toradex.com
> Subject: RE: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> configurations
> 
> > -----Original Message-----
> > From: Lucas Stach <l.stach@pengutronix.de>
> > Sent: 2022年11月1日 16:45
> > To: Shawn Guo <shawnguo@kernel.org>; Hongxing Zhu
> > <hongxing.zhu@nxp.com>
> > Cc: marex@denx.de; tharvey@gateworks.com; vkoul@kernel.org;
> > bhelgaas@google.com; lorenzo.pieralisi@arm.com;
> > alexander.stein@ew.tq-group.com; richard.leitner@linux.dev;
> > devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> > Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
> > configurations
> >
> > Hi Shawn, Richard,
> >
> > Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be
> > > > used as i.MX8MP PCIe reference clock.
> > > >
> > > > The following properties of PHY dts node should be changed accordingly.
> > > >   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > >   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > > >
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > >
> > > Applied, thanks!
> >
> > Sorry for the late reply, but I'm not really happy with the fact that
> > the PLL is now unconditionally enabled, even though it is only needed
> > when there is no external reference clock source.
> > I fear that this will be hard to correct later on as the DT
> > abstraction is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference
> > clock for the PHY, but the PLL generated clock, which isn't properly exposed
> with this series.
> Hi Lucas:
> First of all, thanks for your comments.
> 
> IMHO, I'm not sure it's proper or not to describe the hardware logic in  the
> PHY node when internal SYSPLL is used as PCIe PHY reference clock.
> So, I'm trying to get some suggestions and used to send out an email to  you
> and Marcel on Sep20.
> 
> Okay, if you think it's not correct to expose IMX8MP_CLK_HSIO_ROOT clock
> out.
> Which clock you are prefer to use as PHY reference clock here?
> 
> Thanks.
> 
> Best Regards
> Richard Zhu
> >
> > I'm not happy to see this going in in the current state and if not too
> > late would like to ask Shawn to remove it from the tree again.
Hi Lucas:
Refer to the "Reference Clock Section" of i.MX8MP PCIe PHY document.
I_pll_refclk_from_syspll clock is used as reference clock when Inner chip
 clock mode is used.

In the current codes, IMX8MP_CLK_HSIO_AXI is source from sys_pll2 clock.
is it reasonable that use it as PCIe reference clock in this scenario here?

Best Regards
Richard Zhu

> >
> > Regards,
> > Lucas
diff mbox series

Patch

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 0e3b6ba22f94..5ad20a8ea25e 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -21,6 +21,16 @@ 
 #define  USB_CLOCK_MODULE_EN	BIT(1)
 #define  PCIE_PHY_APB_RST	BIT(4)
 #define  PCIE_PHY_INIT_RST	BIT(5)
+#define GPR_REG2		0x8
+#define  P_PLL_MASK		GENMASK(5, 0)
+#define  M_PLL_MASK		GENMASK(15, 6)
+#define  S_PLL_MASK		GENMASK(18, 16)
+#define  P_PLL			(0xc << 0)
+#define  M_PLL			(0x320 << 6)
+#define  S_PLL			(0x4 << 16)
+#define GPR_REG3		0xc
+#define  PLL_CKE		BIT(17)
+#define  PLL_RST		BIT(31)
 
 struct imx8mp_blk_ctrl_domain;
 
@@ -86,6 +96,18 @@  static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
 	case IMX8MP_HSIOBLK_PD_PCIE_PHY:
 		regmap_set_bits(bc->regmap, GPR_REG0,
 				PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+
+		/* Set the PLL configurations, P = 12, M = 800, S = 4. */
+		regmap_update_bits(bc->regmap, GPR_REG2,
+				   P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
+				   P_PLL | M_PLL | S_PLL);
+		udelay(1);
+
+		regmap_update_bits(bc->regmap, GPR_REG3, PLL_RST, PLL_RST);
+		udelay(10);
+
+		/* Set 1b'1 to pll_cke of GPR_REG3 */
+		regmap_update_bits(bc->regmap, GPR_REG3, PLL_CKE, PLL_CKE);
 		break;
 	default:
 		break;