[6/6] perf vendor events amd: Add Zen 4 memory controller events
Commit Message
Make the jevents parser aware of the Unified Memory Controller (UMC) PMU
and add events taken from Section 8.2.1 "UMC Performance Monitor Events"
of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
processors. The events capture UMC command activity such as CAS, ACTIVATE,
PRECHARGE etc. while the metrics derive data bus utilization and memory
bandwidth out of these events.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
.../arch/x86/amdzen4/memory-controller.json | 101 ++++++++++++++++++
.../arch/x86/amdzen4/recommended.json | 84 +++++++++++++++
tools/perf/pmu-events/jevents.py | 2 +
3 files changed, 187 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
Comments
On Tue, Jul 18, 2023 at 11:58 PM Sandipan Das <sandipan.das@amd.com> wrote:
>
> Make the jevents parser aware of the Unified Memory Controller (UMC) PMU
> and add events taken from Section 8.2.1 "UMC Performance Monitor Events"
> of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
> processors. The events capture UMC command activity such as CAS, ACTIVATE,
> PRECHARGE etc. while the metrics derive data bus utilization and memory
> bandwidth out of these events.
>
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
> ---
> .../arch/x86/amdzen4/memory-controller.json | 101 ++++++++++++++++++
> .../arch/x86/amdzen4/recommended.json | 84 +++++++++++++++
> tools/perf/pmu-events/jevents.py | 2 +
> 3 files changed, 187 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>
> diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
> new file mode 100644
> index 000000000000..55263e5e4f69
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
> @@ -0,0 +1,101 @@
> +[
> + {
> + "EventName": "umc_mem_clk",
> + "PublicDescription": "Number of memory clock cycles.",
> + "EventCode": "0x00",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
nit: Why use UMCPMC and then rewrite to amd_umc, why not just use "amd_umc" ?
Thanks,
Ian
> + },
> + {
> + "EventName": "umc_act_cmd.all",
> + "PublicDescription": "Number of ACTIVATE commands sent.",
> + "EventCode": "0x05",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_act_cmd.rd",
> + "PublicDescription": "Number of ACTIVATE commands sent for reads.",
> + "EventCode": "0x05",
> + "RdWrMask": "0x1",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_act_cmd.wr",
> + "PublicDescription": "Number of ACTIVATE commands sent for writes.",
> + "EventCode": "0x05",
> + "RdWrMask": "0x2",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_pchg_cmd.all",
> + "PublicDescription": "Number of PRECHARGE commands sent.",
> + "EventCode": "0x06",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_pchg_cmd.rd",
> + "PublicDescription": "Number of PRECHARGE commands sent for reads.",
> + "EventCode": "0x06",
> + "RdWrMask": "0x1",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_pchg_cmd.wr",
> + "PublicDescription": "Number of PRECHARGE commands sent for writes.",
> + "EventCode": "0x06",
> + "RdWrMask": "0x2",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_cas_cmd.all",
> + "PublicDescription": "Number of CAS commands sent.",
> + "EventCode": "0x0a",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_cas_cmd.rd",
> + "PublicDescription": "Number of CAS commands sent for reads.",
> + "EventCode": "0x0a",
> + "RdWrMask": "0x1",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_cas_cmd.wr",
> + "PublicDescription": "Number of CAS commands sent for writes.",
> + "EventCode": "0x0a",
> + "RdWrMask": "0x2",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_data_slot_clks.all",
> + "PublicDescription": "Number of clocks used by the data bus.",
> + "EventCode": "0x14",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_data_slot_clks.rd",
> + "PublicDescription": "Number of clocks used by the data bus for reads.",
> + "EventCode": "0x14",
> + "RdWrMask": "0x1",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + },
> + {
> + "EventName": "umc_data_slot_clks.wr",
> + "PublicDescription": "Number of clocks used by the data bus for writes.",
> + "EventCode": "0x14",
> + "RdWrMask": "0x2",
> + "PerPkg": "1",
> + "Unit": "UMCPMC"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json b/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json
> index 5e6a793acf7b..96e06401c6cb 100644
> --- a/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json
> +++ b/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json
> @@ -330,5 +330,89 @@
> "MetricGroup": "data_fabric",
> "PerPkg": "1",
> "ScaleUnit": "6.103515625e-5MiB"
> + },
> + {
> + "MetricName": "umc_data_bus_utilization",
> + "BriefDescription": "Memory controller data bus utilization.",
> + "MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "100%"
> + },
> + {
> + "MetricName": "umc_cas_cmd_rate",
> + "BriefDescription": "Memory controller CAS command rate.",
> + "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1"
> + },
> + {
> + "MetricName": "umc_cas_cmd_read_ratio",
> + "BriefDescription": "Ratio of memory controller CAS commands for reads.",
> + "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "100%"
> + },
> + {
> + "MetricName": "umc_cas_cmd_write_ratio",
> + "BriefDescription": "Ratio of memory controller CAS commands for writes.",
> + "MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "100%"
> + },
> + {
> + "MetricName": "umc_mem_read_bandwidth",
> + "BriefDescription": "Estimated memory read bandwidth.",
> + "MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "1MB/s"
> + },
> + {
> + "MetricName": "umc_mem_write_bandwidth",
> + "BriefDescription": "Estimated memory write bandwidth.",
> + "MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "1MB/s"
> + },
> + {
> + "MetricName": "umc_mem_bandwidth",
> + "BriefDescription": "Estimated combined memory bandwidth.",
> + "MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "1MB/s"
> + },
> + {
> + "MetricName": "umc_cas_cmd_read_ratio",
> + "BriefDescription": "Ratio of memory controller CAS commands for reads.",
> + "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1",
> + "ScaleUnit": "100%"
> + },
> + {
> + "MetricName": "umc_cas_cmd_rate",
> + "BriefDescription": "Memory controller CAS command rate.",
> + "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1"
> + },
> + {
> + "MetricName": "umc_activate_cmd_rate",
> + "BriefDescription": "Memory controller ACTIVATE command rate.",
> + "MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1"
> + },
> + {
> + "MetricName": "umc_precharge_cmd_rate",
> + "BriefDescription": "Memory controller PRECHARGE command rate.",
> + "MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
> + "MetricGroup": "memory_controller",
> + "PerPkg": "1"
> }
> ]
> diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
> index 12e80bb7939b..c2a5728253db 100755
> --- a/tools/perf/pmu-events/jevents.py
> +++ b/tools/perf/pmu-events/jevents.py
> @@ -272,6 +272,7 @@ class JsonEvent:
> 'imx8_ddr': 'imx8_ddr',
> 'L3PMC': 'amd_l3',
> 'DFPMC': 'amd_df',
> + 'UMCPMC': 'amd_umc',
> 'cpu_core': 'cpu_core',
> 'cpu_atom': 'cpu_atom',
> }
> @@ -330,6 +331,7 @@ class JsonEvent:
> ('Invert', 'inv='),
> ('SampleAfterValue', 'period='),
> ('UMask', 'umask='),
> + ('RdWrMask', 'rdwrmask='),
> ]
> for key, value in event_fields:
> if key in jd and jd[key] != '0':
> --
> 2.34.1
>
On 7/19/2023 9:42 PM, Ian Rogers wrote:
> On Tue, Jul 18, 2023 at 11:58 PM Sandipan Das <sandipan.das@amd.com> wrote:
>>
>> Make the jevents parser aware of the Unified Memory Controller (UMC) PMU
>> and add events taken from Section 8.2.1 "UMC Performance Monitor Events"
>> of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
>> processors. The events capture UMC command activity such as CAS, ACTIVATE,
>> PRECHARGE etc. while the metrics derive data bus utilization and memory
>> bandwidth out of these events.
>>
>> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
>
> Acked-by: Ian Rogers <irogers@google.com>
>
>> ---
>> .../arch/x86/amdzen4/memory-controller.json | 101 ++++++++++++++++++
>> .../arch/x86/amdzen4/recommended.json | 84 +++++++++++++++
>> tools/perf/pmu-events/jevents.py | 2 +
>> 3 files changed, 187 insertions(+)
>> create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>>
>> diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>> new file mode 100644
>> index 000000000000..55263e5e4f69
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>> @@ -0,0 +1,101 @@
>> +[
>> + {
>> + "EventName": "umc_mem_clk",
>> + "PublicDescription": "Number of memory clock cycles.",
>> + "EventCode": "0x00",
>> + "PerPkg": "1",
>> + "Unit": "UMCPMC"
>
> nit: Why use UMCPMC and then rewrite to amd_umc, why not just use "amd_umc" ?
>
I followed the convention that has been historically used for AMD uncore PMUs e.g.
the "Unit" for amd_df is "DFPMC" and for amd_l3 is "L3PMC". I do agree that its
simpler to use the same naming so will change this. If you prefer, I can send out
a separate patch to change the unit naming for amd_df and amd_l3.
- Sandipan
On Wed, Jul 19, 2023 at 10:23 PM Sandipan Das <sandipan.das@amd.com> wrote:
>
> On 7/19/2023 9:42 PM, Ian Rogers wrote:
> > On Tue, Jul 18, 2023 at 11:58 PM Sandipan Das <sandipan.das@amd.com> wrote:
> >>
> >> Make the jevents parser aware of the Unified Memory Controller (UMC) PMU
> >> and add events taken from Section 8.2.1 "UMC Performance Monitor Events"
> >> of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
> >> processors. The events capture UMC command activity such as CAS, ACTIVATE,
> >> PRECHARGE etc. while the metrics derive data bus utilization and memory
> >> bandwidth out of these events.
> >>
> >> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> >
> > Acked-by: Ian Rogers <irogers@google.com>
> >
> >> ---
> >> .../arch/x86/amdzen4/memory-controller.json | 101 ++++++++++++++++++
> >> .../arch/x86/amdzen4/recommended.json | 84 +++++++++++++++
> >> tools/perf/pmu-events/jevents.py | 2 +
> >> 3 files changed, 187 insertions(+)
> >> create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
> >>
> >> diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
> >> new file mode 100644
> >> index 000000000000..55263e5e4f69
> >> --- /dev/null
> >> +++ b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
> >> @@ -0,0 +1,101 @@
> >> +[
> >> + {
> >> + "EventName": "umc_mem_clk",
> >> + "PublicDescription": "Number of memory clock cycles.",
> >> + "EventCode": "0x00",
> >> + "PerPkg": "1",
> >> + "Unit": "UMCPMC"
> >
> > nit: Why use UMCPMC and then rewrite to amd_umc, why not just use "amd_umc" ?
> >
>
> I followed the convention that has been historically used for AMD uncore PMUs e.g.
> the "Unit" for amd_df is "DFPMC" and for amd_l3 is "L3PMC". I do agree that its
> simpler to use the same naming so will change this. If you prefer, I can send out
> a separate patch to change the unit naming for amd_df and amd_l3.
Thanks for the explanation. I don't mind but it is nicer to have fewer
renames imo. If we get rid of one, perhaps we can get rid of them all?
Perhaps merge this and follow up with simplification.
Thanks,
Ian
> - Sandipan
>
On 7/20/2023 9:20 PM, Ian Rogers wrote:
> On Wed, Jul 19, 2023 at 10:23 PM Sandipan Das <sandipan.das@amd.com> wrote:
>>
>> On 7/19/2023 9:42 PM, Ian Rogers wrote:
>>> On Tue, Jul 18, 2023 at 11:58 PM Sandipan Das <sandipan.das@amd.com> wrote:
>>>>
>>>> Make the jevents parser aware of the Unified Memory Controller (UMC) PMU
>>>> and add events taken from Section 8.2.1 "UMC Performance Monitor Events"
>>>> of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
>>>> processors. The events capture UMC command activity such as CAS, ACTIVATE,
>>>> PRECHARGE etc. while the metrics derive data bus utilization and memory
>>>> bandwidth out of these events.
>>>>
>>>> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
>>>
>>> Acked-by: Ian Rogers <irogers@google.com>
>>>
>>>> ---
>>>> .../arch/x86/amdzen4/memory-controller.json | 101 ++++++++++++++++++
>>>> .../arch/x86/amdzen4/recommended.json | 84 +++++++++++++++
>>>> tools/perf/pmu-events/jevents.py | 2 +
>>>> 3 files changed, 187 insertions(+)
>>>> create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>>>>
>>>> diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>>>> new file mode 100644
>>>> index 000000000000..55263e5e4f69
>>>> --- /dev/null
>>>> +++ b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json
>>>> @@ -0,0 +1,101 @@
>>>> +[
>>>> + {
>>>> + "EventName": "umc_mem_clk",
>>>> + "PublicDescription": "Number of memory clock cycles.",
>>>> + "EventCode": "0x00",
>>>> + "PerPkg": "1",
>>>> + "Unit": "UMCPMC"
>>>
>>> nit: Why use UMCPMC and then rewrite to amd_umc, why not just use "amd_umc" ?
>>>
>>
>> I followed the convention that has been historically used for AMD uncore PMUs e.g.
>> the "Unit" for amd_df is "DFPMC" and for amd_l3 is "L3PMC". I do agree that its
>> simpler to use the same naming so will change this. If you prefer, I can send out
>> a separate patch to change the unit naming for amd_df and amd_l3.
>
> Thanks for the explanation. I don't mind but it is nicer to have fewer
> renames imo. If we get rid of one, perhaps we can get rid of them all?
> Perhaps merge this and follow up with simplification.
>
Sure, sounds good.
- Sandipan
new file mode 100644
@@ -0,0 +1,101 @@
+[
+ {
+ "EventName": "umc_mem_clk",
+ "PublicDescription": "Number of memory clock cycles.",
+ "EventCode": "0x00",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_act_cmd.all",
+ "PublicDescription": "Number of ACTIVATE commands sent.",
+ "EventCode": "0x05",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_act_cmd.rd",
+ "PublicDescription": "Number of ACTIVATE commands sent for reads.",
+ "EventCode": "0x05",
+ "RdWrMask": "0x1",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_act_cmd.wr",
+ "PublicDescription": "Number of ACTIVATE commands sent for writes.",
+ "EventCode": "0x05",
+ "RdWrMask": "0x2",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_pchg_cmd.all",
+ "PublicDescription": "Number of PRECHARGE commands sent.",
+ "EventCode": "0x06",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_pchg_cmd.rd",
+ "PublicDescription": "Number of PRECHARGE commands sent for reads.",
+ "EventCode": "0x06",
+ "RdWrMask": "0x1",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_pchg_cmd.wr",
+ "PublicDescription": "Number of PRECHARGE commands sent for writes.",
+ "EventCode": "0x06",
+ "RdWrMask": "0x2",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_cas_cmd.all",
+ "PublicDescription": "Number of CAS commands sent.",
+ "EventCode": "0x0a",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_cas_cmd.rd",
+ "PublicDescription": "Number of CAS commands sent for reads.",
+ "EventCode": "0x0a",
+ "RdWrMask": "0x1",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_cas_cmd.wr",
+ "PublicDescription": "Number of CAS commands sent for writes.",
+ "EventCode": "0x0a",
+ "RdWrMask": "0x2",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_data_slot_clks.all",
+ "PublicDescription": "Number of clocks used by the data bus.",
+ "EventCode": "0x14",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_data_slot_clks.rd",
+ "PublicDescription": "Number of clocks used by the data bus for reads.",
+ "EventCode": "0x14",
+ "RdWrMask": "0x1",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ },
+ {
+ "EventName": "umc_data_slot_clks.wr",
+ "PublicDescription": "Number of clocks used by the data bus for writes.",
+ "EventCode": "0x14",
+ "RdWrMask": "0x2",
+ "PerPkg": "1",
+ "Unit": "UMCPMC"
+ }
+]
@@ -330,5 +330,89 @@
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
+ },
+ {
+ "MetricName": "umc_data_bus_utilization",
+ "BriefDescription": "Memory controller data bus utilization.",
+ "MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricName": "umc_cas_cmd_rate",
+ "BriefDescription": "Memory controller CAS command rate.",
+ "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1"
+ },
+ {
+ "MetricName": "umc_cas_cmd_read_ratio",
+ "BriefDescription": "Ratio of memory controller CAS commands for reads.",
+ "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricName": "umc_cas_cmd_write_ratio",
+ "BriefDescription": "Ratio of memory controller CAS commands for writes.",
+ "MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricName": "umc_mem_read_bandwidth",
+ "BriefDescription": "Estimated memory read bandwidth.",
+ "MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "MetricName": "umc_mem_write_bandwidth",
+ "BriefDescription": "Estimated memory write bandwidth.",
+ "MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "MetricName": "umc_mem_bandwidth",
+ "BriefDescription": "Estimated combined memory bandwidth.",
+ "MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "1MB/s"
+ },
+ {
+ "MetricName": "umc_cas_cmd_read_ratio",
+ "BriefDescription": "Ratio of memory controller CAS commands for reads.",
+ "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricName": "umc_cas_cmd_rate",
+ "BriefDescription": "Memory controller CAS command rate.",
+ "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1"
+ },
+ {
+ "MetricName": "umc_activate_cmd_rate",
+ "BriefDescription": "Memory controller ACTIVATE command rate.",
+ "MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1"
+ },
+ {
+ "MetricName": "umc_precharge_cmd_rate",
+ "BriefDescription": "Memory controller PRECHARGE command rate.",
+ "MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
+ "MetricGroup": "memory_controller",
+ "PerPkg": "1"
}
]
@@ -272,6 +272,7 @@ class JsonEvent:
'imx8_ddr': 'imx8_ddr',
'L3PMC': 'amd_l3',
'DFPMC': 'amd_df',
+ 'UMCPMC': 'amd_umc',
'cpu_core': 'cpu_core',
'cpu_atom': 'cpu_atom',
}
@@ -330,6 +331,7 @@ class JsonEvent:
('Invert', 'inv='),
('SampleAfterValue', 'period='),
('UMask', 'umask='),
+ ('RdWrMask', 'rdwrmask='),
]
for key, value in event_fields:
if key in jd and jd[key] != '0':