Message ID | a782c749ecf8192a4f89ba270e30c7fb1d245c51.1689580812.git.Sandor.yu@nxp.com |
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Series |
Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ
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Commit Message
Sandor Yu
July 17, 2023, 8:03 a.m. UTC
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
Comments
On Mon, 17 Jul 2023 16:03:51 +0800, Sandor Yu wrote: > Add bindings for Freescale iMX8MQ DP and HDMI PHY. > > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> > --- > .../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 53 +++++++++++++++++++ > 1 file changed, 53 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file mode 100644 index 000000000000..917f113503dc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mq-dp-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC + +maintainers: + - Sandor Yu <sandor.yu@nxp.com> + +properties: + compatible: + enum: + - fsl,imx8mq-dp-phy + - fsl,imx8mq-hdmi-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: PHY reference clock. + - description: APB clock. + + clock-names: + items: + - const: ref + - const: apb + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mq-clock.h> + #include <dt-bindings/phy/phy.h> + dp_phy: phy@32c00000 { + compatible = "fsl,imx8mq-dp-phy"; + reg = <0x32c00000 0x100000>; + #phy-cells = <0>; + clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ref", "apb"; + };