[v4,6/6] mmc: sdhci-cadence: Add debug option for SD6 controller

  From: Jayanthi Annadurai <jannadurai@marvell.com>

Add support dumping PHY and host controller register configuration
if debug config enabled.

Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
 drivers/mmc/host/sdhci-cadence.c | 156 ++++++++++++++++++++++++++++++-
 1 file changed, 155 insertions(+), 1 deletion(-)
  

Hi Piyush,

kernel test robot noticed the following build errors:

[auto build test ERROR on ulf-hansson-mmc-mirror/next]
[also build test ERROR on robh/for-next linus/master v6.5-rc2 next-20230718]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Piyush-Malgujar/mmc-sdhci-cadence-Rename-functions-structures-to-SD4-specific/20230718-175102
base:   https://git.linaro.org/people/ulf.hansson/mmc-mirror.git next
patch link:    https://lore.kernel.org/r/20230717125146.16791-7-pmalgujar%40marvell.com
patch subject: [PATCH v4 6/6] mmc: sdhci-cadence: Add debug option for SD6 controller
config: csky-randconfig-r023-20230718 (https://download.01.org/0day-ci/archive/20230718/202307182343.ZsoiCcbg-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230718/202307182343.ZsoiCcbg-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307182343.ZsoiCcbg-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/mmc/host/sdhci-cadence.c: In function 'sdhci_cdns_sd6_dump':
>> drivers/mmc/host/sdhci-cadence.c:1066:9: error: too few arguments to function 'sdhci_cdns_sd6_phy_dump'
    1066 |         sdhci_cdns_sd6_phy_dump(phy);
         |         ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/mmc/host/sdhci-cadence.c:981:6: note: declared here
     981 | void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy,
         |      ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/mmc/host/sdhci-cadence.c: In function 'sdhci_cdns_probe':
   drivers/mmc/host/sdhci-cadence.c:1973:9: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
    1973 |         static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
         |         ^~~~~~


vim +/sdhci_cdns_sd6_phy_dump +1066 drivers/mmc/host/sdhci-cadence.c

  1059	
  1060	static
  1061	void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv, struct sdhci_host *host)
  1062	{
  1063		struct sdhci_cdns_sd6_phy *phy = priv->phy;
  1064		int id;
  1065	
> 1066		sdhci_cdns_sd6_phy_dump(phy);
  1067	
  1068		dev_dbg(mmc_dev(host->mmc), "Host controller Register Dump\n");
  1069		for (id = 0; id < 14; id++) {
  1070			dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
  1071				readl(priv->hrs_addr + (id * 4)));
  1072		}
  1073	
  1074		id = 29;
  1075		dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
  1076			readl(priv->hrs_addr + (id * 4)));
  1077		id = 30;
  1078		dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
  1079			readl(priv->hrs_addr + (id * 4)));
  1080	
  1081		for (id = 0; id < 27; id++) {
  1082			dev_dbg(mmc_dev(host->mmc), "SRS%d 0x%x\n", id,
  1083				readl(priv->hrs_addr + 0x200 + (id * 4)));
  1084		}
  1085	
  1086		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
  1087			sdhci_cdns_sd6_read_phy_reg(priv,
  1088						    SDHCI_CDNS_SD6_PHY_DQS_TIMING));
  1089		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
  1090			sdhci_cdns_sd6_read_phy_reg(priv,
  1091						    SDHCI_CDNS_SD6_PHY_GATE_LPBK));
  1092		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
  1093			sdhci_cdns_sd6_read_phy_reg(priv,
  1094						    SDHCI_CDNS_SD6_PHY_DLL_MASTER));
  1095		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
  1096			sdhci_cdns_sd6_read_phy_reg(priv,
  1097						    SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
  1098		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
  1099			sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
  1100		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
  1101			sdhci_cdns_sd6_read_phy_reg(priv,
  1102						    SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
  1103		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
  1104			sdhci_cdns_sd6_read_phy_reg(priv,
  1105						    SDHCI_CDNS_SD6_PHY_DQ_TIMING));
  1106		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
  1107			sdhci_cdns_sd6_read_phy_reg(priv,
  1108						    SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
  1109		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
  1110			sdhci_cdns_sd6_read_phy_reg(priv,
  1111						    SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
  1112		dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
  1113			sdhci_cdns_sd6_read_phy_reg(priv,
  1114						    SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
  1115	}
  1116
  

On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@marvell.com>
> 
> Add support dumping PHY and host controller register configuration
> if debug config enabled.
> 
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
>  drivers/mmc/host/sdhci-cadence.c | 156 ++++++++++++++++++++++++++++++-
>  1 file changed, 155 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index f1e597219c603f3921439cedb22dcb2884abe68d..337a97bf906137f0eac4122cdd603f25df7ae8d9 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -116,6 +116,10 @@
>  #define	SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY		GENMASK(15, 8)
>  #define	SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY		GENMASK(7, 0)
>  
> +#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0				0x201C
> +#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1				0x2020
> +#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2				0x2024
> +
>  #define SDHCI_CDNS_SD6_PHY_CTRL					0x2080
>  #define	SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING		GENMASK(9, 4)
>  
> @@ -813,7 +817,7 @@ static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
>  }
>  
>  static int sdhci_cdns_sd4_write_phy_reg(struct sdhci_cdns_priv *priv,
> -					u8 addr, u8 data)
> +				    u8 addr, u8 data)

Whitespace change should be done when renaming the function.

>  {
>  	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
>  	u32 tmp;
> @@ -971,6 +975,154 @@ static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
>  	}
>  }
>  
> +#if defined(DEBUG) || IS_ENABLED(CONFIG_DYNAMIC_DEBUG)

Not sure what madness caused my comment last version, but this
is actually redundant.  If the condition above is not true
then the whole thing will get optimized away anyway. i.e.
conditional compilation is not needed here.

> +
> +static
> +void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy,
> +			     struct sdhci_host *host)
> +{
> +	dev_dbg(mmc_dev(host->mmc), "PHY Timings\n");
> +	dev_dbg(mmc_dev(host->mmc), "mode %d t_sdclk %d\n", phy->mode,
> +		phy->t_sdclk);
> +
> +	dev_dbg(mmc_dev(host->mmc), "cp_clk_wr_delay %d\n",
> +		phy->settings.cp_clk_wr_delay);
> +	dev_dbg(mmc_dev(host->mmc), "cp_clk_wrdqs_delay %d\n",
> +		phy->settings.cp_clk_wrdqs_delay);
> +	dev_dbg(mmc_dev(host->mmc), "cp_data_select_oe_end %d\n",
> +		phy->settings.cp_data_select_oe_end);
> +	dev_dbg(mmc_dev(host->mmc), "cp_dll_bypass_mode %d\n",
> +		phy->settings.cp_dll_bypass_mode);
> +	dev_dbg(mmc_dev(host->mmc), "cp_dll_locked_mode %d\n",
> +		phy->settings.cp_dll_locked_mode);
> +	dev_dbg(mmc_dev(host->mmc), "cp_dll_start_point %d\n",
> +		phy->settings.cp_dll_start_point);
> +	dev_dbg(mmc_dev(host->mmc), "cp_io_mask_always_on %d\n",
> +		phy->settings.cp_io_mask_always_on);
> +	dev_dbg(mmc_dev(host->mmc), "cp_io_mask_end %d\n",
> +		phy->settings.cp_io_mask_end);
> +	dev_dbg(mmc_dev(host->mmc), "cp_io_mask_start %d\n",
> +		phy->settings.cp_io_mask_start);
> +	dev_dbg(mmc_dev(host->mmc), "cp_rd_del_sel %d\n",
> +		phy->settings.cp_rd_del_sel);
> +	dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_cmd_delay %d\n",
> +		phy->settings.cp_read_dqs_cmd_delay);
> +	dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_delay %d\n",
> +		phy->settings.cp_read_dqs_delay);
> +	dev_dbg(mmc_dev(host->mmc), "cp_sw_half_cycle_shift %d\n",
> +		phy->settings.cp_sw_half_cycle_shift);
> +	dev_dbg(mmc_dev(host->mmc), "cp_sync_method %d\n",
> +		phy->settings.cp_sync_method);
> +	dev_dbg(mmc_dev(host->mmc), "cp_use_ext_lpbk_dqs %d\n",
> +		phy->settings.cp_use_ext_lpbk_dqs);
> +	dev_dbg(mmc_dev(host->mmc), "cp_use_lpbk_dqs %d\n",
> +		phy->settings.cp_use_lpbk_dqs);
> +	dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs %d\n",
> +		phy->settings.cp_use_phony_dqs);
> +	dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs_cmd %d\n",
> +		phy->settings.cp_use_phony_dqs_cmd);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_extended_rd_mode %d\n",
> +		phy->settings.sdhc_extended_rd_mode);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_extended_wr_mode %d\n",
> +		phy->settings.sdhc_extended_wr_mode);
> +
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_hcsdclkadj %d\n",
> +		phy->settings.sdhc_hcsdclkadj);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_idelay_val %d\n",
> +		phy->settings.sdhc_idelay_val);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_rdcmd_en %d\n",
> +		phy->settings.sdhc_rdcmd_en);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_rddata_en %d\n",
> +		phy->settings.sdhc_rddata_en);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_rw_compensate %d\n",
> +		phy->settings.sdhc_rw_compensate);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsh %d\n",
> +		phy->settings.sdhc_sdcfsh);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsl %d\n",
> +		phy->settings.sdhc_sdcfsl);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd0_dly %d %d\n",
> +		phy->settings.sdhc_wrcmd0_dly,
> +		phy->settings.sdhc_wrcmd0_sdclk_dly);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd1_dly %d %d\n",
> +		phy->settings.sdhc_wrcmd1_dly,
> +		phy->settings.sdhc_wrcmd1_sdclk_dly);
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata0_dly %d %d\n",
> +		phy->settings.sdhc_wrdata0_dly,
> +		phy->settings.sdhc_wrdata0_sdclk_dly);
> +
> +	dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata1_dly %d %d\n",
> +		phy->settings.sdhc_wrdata1_dly,
> +		phy->settings.sdhc_wrdata1_sdclk_dly);
> +	dev_dbg(mmc_dev(host->mmc), "hs200_tune_val %d\n",
> +		phy->settings.hs200_tune_val);
> +}
> +
> +static
> +void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv, struct sdhci_host *host)
> +{
> +	struct sdhci_cdns_sd6_phy *phy = priv->phy;
> +	int id;
> +
> +	sdhci_cdns_sd6_phy_dump(phy);

As the robot pointed out, that should be:

	sdhci_cdns_sd6_phy_dump(phy, host);

> +
> +	dev_dbg(mmc_dev(host->mmc), "Host controller Register Dump\n");
> +	for (id = 0; id < 14; id++) {
> +		dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
> +			readl(priv->hrs_addr + (id * 4)));
> +	}
> +
> +	id = 29;
> +	dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
> +		readl(priv->hrs_addr + (id * 4)));
> +	id = 30;
> +	dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
> +		readl(priv->hrs_addr + (id * 4)));
> +
> +	for (id = 0; id < 27; id++) {
> +		dev_dbg(mmc_dev(host->mmc), "SRS%d 0x%x\n", id,
> +			readl(priv->hrs_addr + 0x200 + (id * 4)));
> +	}
> +
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DQS_TIMING));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_GATE_LPBK));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DLL_MASTER));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DQ_TIMING));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
> +	dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
> +		sdhci_cdns_sd6_read_phy_reg(priv,
> +					    SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
> +}
> +
> +#else
> +
> +static inline void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv,
> +				       struct sdhci_host *host)
> +{
> +}
> +
> +#endif
> +
>  static
>  int sdhci_cdns_sd6_get_delay_params(struct device *dev,
>  				    struct sdhci_cdns_priv *priv)
> @@ -1322,6 +1474,8 @@ static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
>  		pr_debug("%s: phy init failed\n", __func__);
>  
>  	sdhci_set_clock(host, clock);
> +
> +	sdhci_cdns_sd6_dump(priv, host);
>  }
>  
>  static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,