diff mbox series

[V4] PCI: qcom: Fixing broken pcie bring up for 2_3_3 configs ops

Message ID 20230717065535.2065582-1-quic_srichara@quicinc.com
State New
Headers
Series [V4] PCI: qcom: Fixing broken pcie bring up for 2_3_3 configs ops |

Commit Message

Sricharan Ramabadhran July 17, 2023, 6:55 a.m. UTC 
  PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074
2_3_3 post_init ops. PCIe slave addr size was initially set
to 0x358, but was wrongly changed to 0x168 as a part of
commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
register definitions"). Fixing it, by using the right macro
PARF_SLV_ADDR_SPACE_SIZE and remove the unused
PARF_SLV_ADDR_SPACE_SIZE_2_3_3.

Without this pcie bring up on IPQ8074 is broken now.

Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
Cc: <Stable@vger.kernel.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 [v4] Fix commit sub and added '<mani@kernel.org>' reviewed-by tag
 [v3] Added reviewed-by tag, fixed subject, commit text
 [v2] Fixed the 'fixes tag' correctly, subject, right macro usage 

 drivers/pci/controller/dwc/pcie-qcom.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Comments

Greg KH July 17, 2023, 1:39 p.m. UTC | #1 
On Mon, Jul 17, 2023 at 12:25:35PM +0530, Sricharan Ramabadhran wrote:
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074
> 2_3_3 post_init ops. PCIe slave addr size was initially set
> to 0x358, but was wrongly changed to 0x168 as a part of
> commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
> register definitions"). Fixing it, by using the right macro
> PARF_SLV_ADDR_SPACE_SIZE and remove the unused
> PARF_SLV_ADDR_SPACE_SIZE_2_3_3.

Note, you do have a full 72 columns to use, no need to make it smaller.

> Without this pcie bring up on IPQ8074 is broken now.

I do not understand, something that used to work now breaks, or this is
preventing a new chip from being "brought up"?

thanks,

greg k-h
Sricharan Ramabadhran July 17, 2023, 5:15 p.m. UTC | #2 
On 7/17/2023 7:09 PM, Greg KH wrote:
> On Mon, Jul 17, 2023 at 12:25:35PM +0530, Sricharan Ramabadhran wrote:
>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074
>> 2_3_3 post_init ops. PCIe slave addr size was initially set
>> to 0x358, but was wrongly changed to 0x168 as a part of
>> commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
>> register definitions"). Fixing it, by using the right macro
>> PARF_SLV_ADDR_SPACE_SIZE and remove the unused
>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
> 
> Note, you do have a full 72 columns to use, no need to make it smaller.

  ok sure

> 
>> Without this pcie bring up on IPQ8074 is broken now.
> 
> I do not understand, something that used to work now breaks, or this is
> preventing a new chip from being "brought up"?
> 

  yes, ipq8074 pcie which was previously working is broken now.
  This patch fixes it.


Regards,
  Sricharan
Dmitry Baryshkov July 17, 2023, 5:53 p.m. UTC | #3 
On Mon, 17 Jul 2023 at 20:16, Sricharan Ramabadhran
<quic_srichara@quicinc.com> wrote:
>
>
>
> On 7/17/2023 7:09 PM, Greg KH wrote:
> > On Mon, Jul 17, 2023 at 12:25:35PM +0530, Sricharan Ramabadhran wrote:
> >> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074
> >> 2_3_3 post_init ops. PCIe slave addr size was initially set
> >> to 0x358, but was wrongly changed to 0x168 as a part of
> >> commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
> >> register definitions"). Fixing it, by using the right macro
> >> PARF_SLV_ADDR_SPACE_SIZE and remove the unused
> >> PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
> >
> > Note, you do have a full 72 columns to use, no need to make it smaller.
>
>   ok sure
>
> >
> >> Without this pcie bring up on IPQ8074 is broken now.
> >
> > I do not understand, something that used to work now breaks, or this is
> > preventing a new chip from being "brought up"?
> >
>
>   yes, ipq8074 pcie which was previously working is broken now.
>   This patch fixes it.

So, you need to describe what is broken and why. Mere "it is broken,
fix it" is not enough.

>
>
> Regards,
>   Sricharan
Sricharan Ramabadhran July 20, 2023, 9:55 a.m. UTC | #4 
On 7/17/2023 11:23 PM, Dmitry Baryshkov wrote:
> On Mon, 17 Jul 2023 at 20:16, Sricharan Ramabadhran
> <quic_srichara@quicinc.com> wrote:
>>
>>
>>
>> On 7/17/2023 7:09 PM, Greg KH wrote:
>>> On Mon, Jul 17, 2023 at 12:25:35PM +0530, Sricharan Ramabadhran wrote:
>>>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074
>>>> 2_3_3 post_init ops. PCIe slave addr size was initially set
>>>> to 0x358, but was wrongly changed to 0x168 as a part of
>>>> commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from
>>>> register definitions"). Fixing it, by using the right macro
>>>> PARF_SLV_ADDR_SPACE_SIZE and remove the unused
>>>> PARF_SLV_ADDR_SPACE_SIZE_2_3_3.
>>>
>>> Note, you do have a full 72 columns to use, no need to make it smaller.
>>
>>    ok sure
>>
>>>
>>>> Without this pcie bring up on IPQ8074 is broken now.
>>>
>>> I do not understand, something that used to work now breaks, or this is
>>> preventing a new chip from being "brought up"?
>>>
>>
>>    yes, ipq8074 pcie which was previously working is broken now.
>>    This patch fixes it.
> 
> So, you need to describe what is broken and why. Mere "it is broken,
> fix it" is not enough.

  ok sure, will change the subject and explicitly state in commit log
  how pcie enumeration is broken up.


Regards,
  Sricharan
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4ab30892f6ef..8418894b3de7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -43,7 +43,6 @@ 
 #define PARF_PHY_REFCLK				0x4c
 #define PARF_CONFIG_BITS			0x50
 #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
 #define PARF_MHI_CLOCK_RESET_CTRL		0x174
 #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
@@ -810,8 +809,7 @@  static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
 	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	u32 val;
 
-	writel(SLV_ADDR_SPACE_SZ,
-		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
+	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
 
 	val = readl(pcie->parf + PARF_PHY_CTRL);
 	val &= ~PHY_TEST_PWR_DOWN;