diff mbox series

[2/2] PCI: layerscape: Add the workaround for lost link capablities during reset

Message ID 20230615164113.2270698-2-Frank.Li@nxp.com
State New
Headers
Series [1/2] PCI: layerscape: Add support for Link down notification |

Commit Message

Frank Li June 15, 2023, 4:41 p.m. UTC 
  From: Xiaowei Bao <xiaowei.bao@nxp.com>

A workaround for the issue where the PCI Express Endpoint (EP) controller
loses the values of the Maximum Link Width and Supported Link Speed from
the Link Capabilities Register, which initially configured by the Reset
Configuration Word (RCW) during a link-down or hot reset event.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Frank Li July 17, 2023, 2:03 p.m. UTC | #1 
On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
> 
> A workaround for the issue where the PCI Express Endpoint (EP) controller
> loses the values of the Maximum Link Width and Supported Link Speed from
> the Link Capabilities Register, which initially configured by the Reset
> Configuration Word (RCW) during a link-down or hot reset event.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---

@lorenzo:
	It is only for layerscape and workaround a small errata.
	Could you please pick this up?

Frank

>  drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 4e4fdd1dfea7..2ef02d827eeb 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -45,6 +45,7 @@ struct ls_pcie_ep {
>  	struct pci_epc_features		*ls_epc;
>  	const struct ls_pcie_ep_drvdata *drvdata;
>  	int				irq;
> +	u32				lnkcap;
>  	bool				big_endian;
>  };
>  
> @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>  	struct ls_pcie_ep *pcie = dev_id;
>  	struct dw_pcie *pci = pcie->pci;
>  	u32 val, cfg;
> +	u8 offset;
>  
>  	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
>  	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>  		return IRQ_NONE;
>  
>  	if (val & PEX_PF0_PME_MES_DR_LUD) {
> +
> +		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +
> +		dw_pcie_dbi_ro_wr_en(pci);
> +		dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> +		dw_pcie_dbi_ro_wr_dis(pci);
> +
>  		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
>  		cfg |= PEX_PF0_CFG_READY;
>  		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>  	struct ls_pcie_ep *pcie;
>  	struct pci_epc_features *ls_epc;
>  	struct resource *dbi_base;
> +	u8 offset;
>  	int ret;
>  
>  	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>  
>  	platform_set_drvdata(pdev, pcie);
>  
> +	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> +
>  	ret = dw_pcie_ep_init(&pci->ep);
>  	if (ret)
>  		return ret;
> -- 
> 2.34.1
>
Rob Herring July 17, 2023, 2:45 p.m. UTC | #2 
On Thu, Jun 15, 2023 at 10:41 AM Frank Li <Frank.Li@nxp.com> wrote:
>
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> A workaround for the issue where the PCI Express Endpoint (EP) controller
> loses the values of the Maximum Link Width and Supported Link Speed from
> the Link Capabilities Register, which initially configured by the Reset
> Configuration Word (RCW) during a link-down or hot reset event.

What makes this Layerscape specific? Seems like something internal to DWC.

>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 4e4fdd1dfea7..2ef02d827eeb 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -45,6 +45,7 @@ struct ls_pcie_ep {
>         struct pci_epc_features         *ls_epc;
>         const struct ls_pcie_ep_drvdata *drvdata;
>         int                             irq;
> +       u32                             lnkcap;
>         bool                            big_endian;
>  };
>
> @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>         struct ls_pcie_ep *pcie = dev_id;
>         struct dw_pcie *pci = pcie->pci;
>         u32 val, cfg;
> +       u8 offset;
>
>         val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
>         ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>                 return IRQ_NONE;
>
>         if (val & PEX_PF0_PME_MES_DR_LUD) {
> +
> +               offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +
> +               dw_pcie_dbi_ro_wr_en(pci);
> +               dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> +               dw_pcie_dbi_ro_wr_dis(pci);
> +
>                 cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
>                 cfg |= PEX_PF0_CFG_READY;
>                 ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>         struct ls_pcie_ep *pcie;
>         struct pci_epc_features *ls_epc;
>         struct resource *dbi_base;
> +       u8 offset;
>         int ret;
>
>         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>
>         platform_set_drvdata(pdev, pcie);
>
> +       offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +       pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> +
>         ret = dw_pcie_ep_init(&pci->ep);
>         if (ret)
>                 return ret;
> --
> 2.34.1
>
Frank Li July 17, 2023, 2:57 p.m. UTC | #3 
On Mon, Jul 17, 2023 at 08:45:14AM -0600, Rob Herring wrote:
> On Thu, Jun 15, 2023 at 10:41 AM Frank Li <Frank.Li@nxp.com> wrote:
> >
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> >
> > A workaround for the issue where the PCI Express Endpoint (EP) controller
> > loses the values of the Maximum Link Width and Supported Link Speed from
> > the Link Capabilities Register, which initially configured by the Reset
> > Configuration Word (RCW) during a link-down or hot reset event.
> 
> What makes this Layerscape specific? Seems like something internal to DWC.

layerscape designed behavor is that LINK speed and width controled by RCW.
But design have been 'defect' when switch to dwc controller, may not
correct connect some wire. So provide an errata, ask software recover such
information when link up/down to align design spec.

For example, RCW config max link is 2lan, after link down/up, DWC reset
to max link to 4lan. So host side get a report, max link is 4 lan. 

It will not impact function, just information miss matched.

Frank

> 
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index 4e4fdd1dfea7..2ef02d827eeb 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -45,6 +45,7 @@ struct ls_pcie_ep {
> >         struct pci_epc_features         *ls_epc;
> >         const struct ls_pcie_ep_drvdata *drvdata;
> >         int                             irq;
> > +       u32                             lnkcap;
> >         bool                            big_endian;
> >  };
> >
> > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> >         struct ls_pcie_ep *pcie = dev_id;
> >         struct dw_pcie *pci = pcie->pci;
> >         u32 val, cfg;
> > +       u8 offset;
> >
> >         val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
> >         ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> > @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> >                 return IRQ_NONE;
> >
> >         if (val & PEX_PF0_PME_MES_DR_LUD) {
> > +
> > +               offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +
> > +               dw_pcie_dbi_ro_wr_en(pci);
> > +               dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> > +               dw_pcie_dbi_ro_wr_dis(pci);
> > +
> >                 cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
> >                 cfg |= PEX_PF0_CFG_READY;
> >                 ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> > @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> >         struct ls_pcie_ep *pcie;
> >         struct pci_epc_features *ls_epc;
> >         struct resource *dbi_base;
> > +       u8 offset;
> >         int ret;
> >
> >         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> >
> >         platform_set_drvdata(pdev, pcie);
> >
> > +       offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +       pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > +
> >         ret = dw_pcie_ep_init(&pci->ep);
> >         if (ret)
> >                 return ret;
> > --
> > 2.34.1
> >
Manivannan Sadhasivam July 17, 2023, 3:59 p.m. UTC | #4 
On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
> 
> A workaround for the issue where the PCI Express Endpoint (EP) controller
> loses the values of the Maximum Link Width and Supported Link Speed from
> the Link Capabilities Register, which initially configured by the Reset
> Configuration Word (RCW) during a link-down or hot reset event.
> 

If this fixes an issue, then there should be a Fixes tag.

> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 4e4fdd1dfea7..2ef02d827eeb 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -45,6 +45,7 @@ struct ls_pcie_ep {
>  	struct pci_epc_features		*ls_epc;
>  	const struct ls_pcie_ep_drvdata *drvdata;
>  	int				irq;
> +	u32				lnkcap;
>  	bool				big_endian;
>  };
>  
> @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>  	struct ls_pcie_ep *pcie = dev_id;
>  	struct dw_pcie *pci = pcie->pci;
>  	u32 val, cfg;
> +	u8 offset;
>  
>  	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
>  	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>  		return IRQ_NONE;
>  
>  	if (val & PEX_PF0_PME_MES_DR_LUD) {
> +

Please add a comment on why the LNKCAP is being restored here.

> +		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +
> +		dw_pcie_dbi_ro_wr_en(pci);
> +		dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);

lnkcap is a 32-bit variable, so you should use dw_pcie_writel_dbi().

- Mani

> +		dw_pcie_dbi_ro_wr_dis(pci);
> +
>  		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
>  		cfg |= PEX_PF0_CFG_READY;
>  		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>  	struct ls_pcie_ep *pcie;
>  	struct pci_epc_features *ls_epc;
>  	struct resource *dbi_base;
> +	u8 offset;
>  	int ret;
>  
>  	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>  
>  	platform_set_drvdata(pdev, pcie);
>  
> +	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> +
>  	ret = dw_pcie_ep_init(&pci->ep);
>  	if (ret)
>  		return ret;
> -- 
> 2.34.1
>
Frank Li July 17, 2023, 6:45 p.m. UTC | #5 
On Mon, Jul 17, 2023 at 09:29:10PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote:
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> > 
> > A workaround for the issue where the PCI Express Endpoint (EP) controller
> > loses the values of the Maximum Link Width and Supported Link Speed from
> > the Link Capabilities Register, which initially configured by the Reset
> > Configuration Word (RCW) during a link-down or hot reset event.
> > 
> 
> If this fixes an issue, then there should be a Fixes tag.

It is not fixed a exist software issue, just workaround a hardwre errata.

> 
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index 4e4fdd1dfea7..2ef02d827eeb 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -45,6 +45,7 @@ struct ls_pcie_ep {
> >  	struct pci_epc_features		*ls_epc;
> >  	const struct ls_pcie_ep_drvdata *drvdata;
> >  	int				irq;
> > +	u32				lnkcap;
> >  	bool				big_endian;
> >  };
> >  
> > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> >  	struct ls_pcie_ep *pcie = dev_id;
> >  	struct dw_pcie *pci = pcie->pci;
> >  	u32 val, cfg;
> > +	u8 offset;
> >  
> >  	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
> >  	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> > @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> >  		return IRQ_NONE;
> >  
> >  	if (val & PEX_PF0_PME_MES_DR_LUD) {
> > +
> 
> Please add a comment on why the LNKCAP is being restored here.
> 
> > +		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +
> > +		dw_pcie_dbi_ro_wr_en(pci);
> > +		dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> 
> lnkcap is a 32-bit variable, so you should use dw_pcie_writel_dbi().
> 
> - Mani
> 
> > +		dw_pcie_dbi_ro_wr_dis(pci);
> > +
> >  		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
> >  		cfg |= PEX_PF0_CFG_READY;
> >  		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> > @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> >  	struct ls_pcie_ep *pcie;
> >  	struct pci_epc_features *ls_epc;
> >  	struct resource *dbi_base;
> > +	u8 offset;
> >  	int ret;
> >  
> >  	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> >  
> >  	platform_set_drvdata(pdev, pcie);
> >  
> > +	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > +	pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > +
> >  	ret = dw_pcie_ep_init(&pci->ep);
> >  	if (ret)
> >  		return ret;
> > -- 
> > 2.34.1
> > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்
Manivannan Sadhasivam July 18, 2023, 5:03 a.m. UTC | #6 
On Mon, Jul 17, 2023 at 02:45:23PM -0400, Frank Li wrote:
> On Mon, Jul 17, 2023 at 09:29:10PM +0530, Manivannan Sadhasivam wrote:
> > On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote:
> > > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > 
> > > A workaround for the issue where the PCI Express Endpoint (EP) controller
> > > loses the values of the Maximum Link Width and Supported Link Speed from
> > > the Link Capabilities Register, which initially configured by the Reset
> > > Configuration Word (RCW) during a link-down or hot reset event.
> > > 
> > 
> > If this fixes an issue, then there should be a Fixes tag.
> 
> It is not fixed a exist software issue, just workaround a hardwre errata.
> 

But the hardware errata is there from the start, right? So technically this
driver doesn't address that so far and so this patch looks like a fix to me.

Plus adding a fixes tag and CCing stable list will allow this patch to be
backported to stable kernels.

- Mani

> > 
> > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > > ---
> > >  drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > index 4e4fdd1dfea7..2ef02d827eeb 100644
> > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > @@ -45,6 +45,7 @@ struct ls_pcie_ep {
> > >  	struct pci_epc_features		*ls_epc;
> > >  	const struct ls_pcie_ep_drvdata *drvdata;
> > >  	int				irq;
> > > +	u32				lnkcap;
> > >  	bool				big_endian;
> > >  };
> > >  
> > > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> > >  	struct ls_pcie_ep *pcie = dev_id;
> > >  	struct dw_pcie *pci = pcie->pci;
> > >  	u32 val, cfg;
> > > +	u8 offset;
> > >  
> > >  	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
> > >  	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> > > @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
> > >  		return IRQ_NONE;
> > >  
> > >  	if (val & PEX_PF0_PME_MES_DR_LUD) {
> > > +
> > 
> > Please add a comment on why the LNKCAP is being restored here.
> > 
> > > +		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > +
> > > +		dw_pcie_dbi_ro_wr_en(pci);
> > > +		dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> > 
> > lnkcap is a 32-bit variable, so you should use dw_pcie_writel_dbi().
> > 
> > - Mani
> > 
> > > +		dw_pcie_dbi_ro_wr_dis(pci);
> > > +
> > >  		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
> > >  		cfg |= PEX_PF0_CFG_READY;
> > >  		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
> > > @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> > >  	struct ls_pcie_ep *pcie;
> > >  	struct pci_epc_features *ls_epc;
> > >  	struct resource *dbi_base;
> > > +	u8 offset;
> > >  	int ret;
> > >  
> > >  	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > > @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> > >  
> > >  	platform_set_drvdata(pdev, pcie);
> > >  
> > > +	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > +	pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > > +
> > >  	ret = dw_pcie_ep_init(&pci->ep);
> > >  	if (ret)
> > >  		return ret;
> > > -- 
> > > 2.34.1
> > > 
> > 
> > -- 
> > மணிவண்ணன் சதாசிவம்
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 4e4fdd1dfea7..2ef02d827eeb 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -45,6 +45,7 @@  struct ls_pcie_ep {
 	struct pci_epc_features		*ls_epc;
 	const struct ls_pcie_ep_drvdata *drvdata;
 	int				irq;
+	u32				lnkcap;
 	bool				big_endian;
 };
 
@@ -73,6 +74,7 @@  static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
 	struct ls_pcie_ep *pcie = dev_id;
 	struct dw_pcie *pci = pcie->pci;
 	u32 val, cfg;
+	u8 offset;
 
 	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
 	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
@@ -81,6 +83,13 @@  static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
 		return IRQ_NONE;
 
 	if (val & PEX_PF0_PME_MES_DR_LUD) {
+
+		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+
+		dw_pcie_dbi_ro_wr_en(pci);
+		dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
+		dw_pcie_dbi_ro_wr_dis(pci);
+
 		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
 		cfg |= PEX_PF0_CFG_READY;
 		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
@@ -216,6 +225,7 @@  static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 	struct ls_pcie_ep *pcie;
 	struct pci_epc_features *ls_epc;
 	struct resource *dbi_base;
+	u8 offset;
 	int ret;
 
 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
@@ -252,6 +262,9 @@  static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, pcie);
 
+	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
+
 	ret = dw_pcie_ep_init(&pci->ep);
 	if (ret)
 		return ret;