@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel PBNDKB instructions.
+
* Add support for Intel SM4 instructions.
* Add support for Intel SM3 instructions.
@@ -1155,6 +1155,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (sha512, SHA512, ANY_SHA512, false),
SUBARCH (sm3, SM3, ANY_SM3, false),
SUBARCH (sm4, SM4, ANY_SM4, false),
+ SUBARCH (pbndkb, PBNDKB, PBNDKB, false),
};
#undef SUBARCH
@@ -211,6 +211,7 @@ accept various extension mnemonics. For example,
@code{sha512},
@code{sm3},
@code{sm4},
+@code{pbndkb},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1641,6 +1642,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
+@item @samp{.pbndkb}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -504,6 +504,7 @@ if [gas_32_check] then {
run_dump_test "sm3-intel"
run_dump_test "sm4"
run_dump_test "sm4-intel"
+ run_list_test "pbndkb-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
new file mode 100644
@@ -0,0 +1,2 @@
+.* Assembler messages:
+.*:6: Error: `pbndkb' is only supported in 64-bit mode
new file mode 100644
@@ -0,0 +1,6 @@
+# Check Illegal PBNDKB instructions
+
+ .allow_index_reg
+ .text
+_start:
+ pbndkb #PBNDKB
new file mode 100644
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 PBNDKB insns (Intel disassembly)
+#source: x86-64-pbndkb.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb
+\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb
new file mode 100644
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: x86_64 PBNDKB insns
+#source: x86-64-pbndkb.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb
+\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb
new file mode 100644
@@ -0,0 +1,9 @@
+# Check 64bit PBNDKB instructions
+
+ .allow_index_reg
+ .text
+_start:
+ pbndkb #PBNDKB
+
+.intel_syntax noprefix
+ pbndkb #PBNDKB
@@ -446,6 +446,8 @@ run_dump_test "x86-64-sm3"
run_dump_test "x86-64-sm3-intel"
run_dump_test "x86-64-sm4"
run_dump_test "x86-64-sm4-intel"
+run_dump_test "x86-64-pbndkb"
+run_dump_test "x86-64-pbndkb-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
@@ -924,6 +924,7 @@ enum
PREFIX_90 = 0,
PREFIX_0F00_REG_6_X86_64,
PREFIX_0F01_REG_0_MOD_3_RM_6,
+ PREFIX_0F01_REG_0_MOD_3_RM_7,
PREFIX_0F01_REG_1_RM_2,
PREFIX_0F01_REG_1_RM_4,
PREFIX_0F01_REG_1_RM_5,
@@ -1198,6 +1199,7 @@ enum
X86_64_0F01_REG_0,
X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
+ X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
X86_64_0F01_REG_1,
X86_64_0F01_REG_1_RM_2_PREFIX_1,
X86_64_0F01_REG_1_RM_2_PREFIX_3,
@@ -2910,6 +2912,11 @@ static const struct dis386 prefix_table[][4] = {
{ X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
},
+ /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
+ {
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
+ },
+
/* PREFIX_0F01_REG_1_RM_2 */
{
{ "clac", { Skip_MODRM }, 0 },
@@ -4194,6 +4201,12 @@ static const struct dis386 x86_64_table[][2] = {
{ "rdmsrlist", { Skip_MODRM }, 0 },
},
+ /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
+ {
+ { Bad_Opcode },
+ { "pbndkb", { Skip_MODRM }, 0 },
+ },
+
/* X86_64_0F01_REG_1 */
{
{ "sidt{Q|Q}", { M }, 0 },
@@ -8190,6 +8203,7 @@ static const struct dis386 rm_table[][8] = {
{ "vmxoff", { Skip_MODRM }, 0 },
{ "pconfig", { Skip_MODRM }, 0 },
{ PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
},
{
/* RM_0F01_REG_1 */
@@ -378,6 +378,7 @@ static bitfield cpu_flags[] =
BITFIELD (SHA512),
BITFIELD (SM3),
BITFIELD (SM4),
+ BITFIELD (PBNDKB),
BITFIELD (MWAITX),
BITFIELD (CLZERO),
BITFIELD (OSPKE),
@@ -241,6 +241,8 @@ enum
CpuSM3,
/* Intel SM4 Instructions support required. */
CpuSM4,
+ /* Intel PBNDKB Instructions support required. */
+ CpuPBNDKB,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -442,6 +444,7 @@ typedef union i386_cpu_flags
unsigned int cpusha512:1;
unsigned int cpusm3:1;
unsigned int cpusm4:1;
+ unsigned int cpupbndkb:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -3397,3 +3397,9 @@ vsm4key4, 0xf3da, SM4, Modrm|Space0F38|Vex|VexVVVV|VexW0|CheckOperandSize|NoSuf,
vsm4rnds4, 0xf2da, SM4, Modrm|Space0F38|Vex|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
// SM4 instructions end.
+
+// PBNDKB instruction.
+
+pbndkb, 0x0f01c7, PBNDKB|x64, NoSuf, {}
+
+// PBNDKB instruction end.