[v2,3/3] RISC-V: Implement archrandom when Zkr is available
Commit Message
The Zkr extension is ratified and provides 16 bits of entropy seed when
reading the SEED CSR.
We can implement arch_get_random_seed_longs() by doing multiple csrrw to
that CSR and filling an unsigned long with valid entropy bits.
Signed-off-by: Samuel Ortiz <sameo@rivosinc.com>
---
arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++++
arch/riscv/include/asm/csr.h | 9 ++++
2 files changed, 79 insertions(+)
create mode 100644 arch/riscv/include/asm/archrandom.h
Comments
On Wed, Jun 28, 2023 at 03:14:35PM +0200, Samuel Ortiz wrote:
> The Zkr extension is ratified and provides 16 bits of entropy seed when
> reading the SEED CSR.
>
> We can implement arch_get_random_seed_longs() by doing multiple csrrw to
> that CSR and filling an unsigned long with valid entropy bits.
>
> Signed-off-by: Samuel Ortiz <sameo@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
On Wed, Jun 28, 2023 at 9:15 AM Samuel Ortiz <sameo@rivosinc.com> wrote:
>
> The Zkr extension is ratified and provides 16 bits of entropy seed when
> reading the SEED CSR.
>
> We can implement arch_get_random_seed_longs() by doing multiple csrrw to
> that CSR and filling an unsigned long with valid entropy bits.
>
> Signed-off-by: Samuel Ortiz <sameo@rivosinc.com>
> ---
> arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++++
> arch/riscv/include/asm/csr.h | 9 ++++
> 2 files changed, 79 insertions(+)
> create mode 100644 arch/riscv/include/asm/archrandom.h
>
> diff --git a/arch/riscv/include/asm/archrandom.h b/arch/riscv/include/asm/archrandom.h
> new file mode 100644
> index 000000000000..8987cd0b891d
> --- /dev/null
> +++ b/arch/riscv/include/asm/archrandom.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Kernel interface for the RISCV arch_random_* functions
> + *
> + * Copyright (c) 2023 by Rivos Inc.
> + *
> + */
> +
> +#ifndef ASM_RISCV_ARCHRANDOM_H
> +#define ASM_RISCV_ARCHRANDOM_H
> +
> +#include <asm/csr.h>
> +
> +#define SEED_RETRY_LOOPS 10
> +
> +static inline bool __must_check csr_seed_long(unsigned long *v)
> +{
> + unsigned int retry = SEED_RETRY_LOOPS, valid_seeds = 0;
> + const int needed_seeds = sizeof(long) / sizeof(u16);
> + u16 *entropy = (u16 *)v;
> +
> + do {
> + /*
> + * The SEED CSR (0x015) must be accessed with a read-write
> + * instruction.
> + */
> + unsigned long csr_seed = csr_swap(CSR_SEED, 0);
> +
> + switch (csr_seed & SEED_OPST_MASK) {
> + case SEED_OPST_ES16:
> + entropy[valid_seeds++] = csr_seed & SEED_ENTROPY_MASK;
> + if (valid_seeds == needed_seeds)
max_longs = 1? needed_seeds only could be 2/4.
> + return true;
> + break;
> +
> + case SEED_OPST_DEAD:
> + pr_err_once("archrandom: Unrecoverable error\n");
Do we need this pr_err? Could we treat it as a return false? Yes, it's
a hardware problem, but not serious.
> + return false;
> +
> + case SEED_OPST_BIST:
> + case SEED_OPST_WAIT:
> + default:
> + continue;
> + }
> + } while (--retry);
> +
> + return false;
> +}
> +
> +static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
> +{
> + return 0;
> +}
> +
> +static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
> +{
> + if (!max_longs )
if (max_longs == 1) ?
> + return 0;
> +
> + /*
> + * If Zkr is supported and csr_seed_long succeeds, we return one long
> + * worth of entropy.
> + */
> + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZKR) && csr_seed_long(v))
> + return 1;
> +
> + return 0;
> +}
> +
> +#endif /* ASM_RISCV_ARCHRANDOM_H */
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index b98b3b6c9da2..7d0ca9082c66 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -389,6 +389,15 @@
> #define CSR_VTYPE 0xc21
> #define CSR_VLENB 0xc22
>
> +/* Scalar Crypto Extension - Entropy */
> +#define CSR_SEED 0x015
> +#define SEED_OPST_MASK _AC(0xC0000000, UL)
> +#define SEED_OPST_BIST _AC(0x00000000, UL)
> +#define SEED_OPST_WAIT _AC(0x40000000, UL)
> +#define SEED_OPST_ES16 _AC(0x80000000, UL)
> +#define SEED_OPST_DEAD _AC(0xC0000000, UL)
> +#define SEED_ENTROPY_MASK _AC(0xFFFF, UL)
> +
> #ifdef CONFIG_RISCV_M_MODE
> # define CSR_STATUS CSR_MSTATUS
> # define CSR_IE CSR_MIE
> --
> 2.41.0
>
Reviewed-by: Guo Ren <guoren@kernel.org>
new file mode 100644
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Kernel interface for the RISCV arch_random_* functions
+ *
+ * Copyright (c) 2023 by Rivos Inc.
+ *
+ */
+
+#ifndef ASM_RISCV_ARCHRANDOM_H
+#define ASM_RISCV_ARCHRANDOM_H
+
+#include <asm/csr.h>
+
+#define SEED_RETRY_LOOPS 10
+
+static inline bool __must_check csr_seed_long(unsigned long *v)
+{
+ unsigned int retry = SEED_RETRY_LOOPS, valid_seeds = 0;
+ const int needed_seeds = sizeof(long) / sizeof(u16);
+ u16 *entropy = (u16 *)v;
+
+ do {
+ /*
+ * The SEED CSR (0x015) must be accessed with a read-write
+ * instruction.
+ */
+ unsigned long csr_seed = csr_swap(CSR_SEED, 0);
+
+ switch (csr_seed & SEED_OPST_MASK) {
+ case SEED_OPST_ES16:
+ entropy[valid_seeds++] = csr_seed & SEED_ENTROPY_MASK;
+ if (valid_seeds == needed_seeds)
+ return true;
+ break;
+
+ case SEED_OPST_DEAD:
+ pr_err_once("archrandom: Unrecoverable error\n");
+ return false;
+
+ case SEED_OPST_BIST:
+ case SEED_OPST_WAIT:
+ default:
+ continue;
+ }
+ } while (--retry);
+
+ return false;
+}
+
+static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
+{
+ return 0;
+}
+
+static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
+{
+ if (!max_longs)
+ return 0;
+
+ /*
+ * If Zkr is supported and csr_seed_long succeeds, we return one long
+ * worth of entropy.
+ */
+ if (riscv_has_extension_likely(RISCV_ISA_EXT_ZKR) && csr_seed_long(v))
+ return 1;
+
+ return 0;
+}
+
+#endif /* ASM_RISCV_ARCHRANDOM_H */
@@ -389,6 +389,15 @@
#define CSR_VTYPE 0xc21
#define CSR_VLENB 0xc22
+/* Scalar Crypto Extension - Entropy */
+#define CSR_SEED 0x015
+#define SEED_OPST_MASK _AC(0xC0000000, UL)
+#define SEED_OPST_BIST _AC(0x00000000, UL)
+#define SEED_OPST_WAIT _AC(0x40000000, UL)
+#define SEED_OPST_ES16 _AC(0x80000000, UL)
+#define SEED_OPST_DEAD _AC(0xC0000000, UL)
+#define SEED_ENTROPY_MASK _AC(0xFFFF, UL)
+
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE