diff mbox series

x86: Enable ENQCMD and UINTR for march=sierraforest.

Message ID 20230704081551.3422387-1-lili.cui@intel.com
State Accepted
Headers
Series x86: Enable ENQCMD and UINTR for march=sierraforest. |

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Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Li, Pan2 via Gcc-patches July 4, 2023, 8:15 a.m. UTC 
  From: Lili Cui <lili.cui@intel.com>

Hi Maintainer,

This patch is to enable ENQCMD and UINTR for march=sierraforest according to Intel ISE.

Bootstrapped and regtested. Ok for trunk? And I will backport this patch to GCC13.

Thanks,
Lili.

Enable ENQCMD and UINTR for march=sierraforest according to Intel ISE
https://cdrdv2.intel.com/v1/dl/getContent/671368

gcc/ChangeLog

	* config/i386/i386.h: Add PTA_ENQCMD and PTA_UINTR to PTA_SIERRAFOREST.
	* doc/invoke.texi: Update new isa to march=sierraforest and grandridge.
---
 gcc/config/i386/i386.h | 2 +-
 gcc/doc/invoke.texi    | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

Comments

Hongtao Liu July 4, 2023, 8:27 a.m. UTC | #1 
On Tue, Jul 4, 2023 at 4:15 PM Cui, Lili <lili.cui@intel.com> wrote:
>
> From: Lili Cui <lili.cui@intel.com>
>
> Hi Maintainer,
>
> This patch is to enable ENQCMD and UINTR for march=sierraforest according to Intel ISE.
>
> Bootstrapped and regtested. Ok for trunk? And I will backport this patch to GCC13.
Ok.
>
> Thanks,
> Lili.
>
> Enable ENQCMD and UINTR for march=sierraforest according to Intel ISE
> https://cdrdv2.intel.com/v1/dl/getContent/671368
>
> gcc/ChangeLog
>
>         * config/i386/i386.h: Add PTA_ENQCMD and PTA_UINTR to PTA_SIERRAFOREST.
>         * doc/invoke.texi: Update new isa to march=sierraforest and grandridge.
> ---
>  gcc/config/i386/i386.h | 2 +-
>  gcc/doc/invoke.texi    | 7 ++++---
>  2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 5ac9c78d3ba..84ebafdf2dc 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2341,7 +2341,7 @@ constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX
>    | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
>    | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
>  constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
> -  | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD;
> +  | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD | PTA_UINTR;
>  constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
>    | PTA_PREFETCHI | PTA_AMX_COMPLEX;
>  constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT;
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 26bcbe26c6c..dc385c1a3d8 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -32559,7 +32559,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
>  XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
>  MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
>  PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
> -AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support.
> +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction set
> +support.
>
>  @item grandridge
>  Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> @@ -32567,8 +32568,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
>  XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
>  MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
>  PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
> -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set
> -support.
> +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD, UINTR and RAOINT
> +instruction set support.
>
>  @item knl
>  Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> --
> 2.25.1
>
Li, Pan2 via Gcc-patches July 4, 2023, 8:45 a.m. UTC | #2 
> -----Original Message-----
> From: Hongtao Liu <crazylht@gmail.com>
> Sent: Tuesday, July 4, 2023 4:27 PM
> To: Cui, Lili <lili.cui@intel.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] x86: Enable ENQCMD and UINTR for march=sierraforest.
> 
> On Tue, Jul 4, 2023 at 4:15 PM Cui, Lili <lili.cui@intel.com> wrote:
> >
> > From: Lili Cui <lili.cui@intel.com>
> >
> > Hi Maintainer,
> >
> > This patch is to enable ENQCMD and UINTR for march=sierraforest
> according to Intel ISE.
> >
> > Bootstrapped and regtested. Ok for trunk? And I will backport this patch to
> GCC13.
> Ok.

Committed and backported to GCC13, thanks.

Regards,
Lili.

> >
> > Thanks,
> > Lili.
> >
> > Enable ENQCMD and UINTR for march=sierraforest according to Intel ISE
> > https://cdrdv2.intel.com/v1/dl/getContent/671368
> >
> > gcc/ChangeLog
> >
> >         * config/i386/i386.h: Add PTA_ENQCMD and PTA_UINTR to
> PTA_SIERRAFOREST.
> >         * doc/invoke.texi: Update new isa to march=sierraforest and
> grandridge.
> > ---
> >  gcc/config/i386/i386.h | 2 +-
> >  gcc/doc/invoke.texi    | 7 ++++---
> >  2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index
> > 5ac9c78d3ba..84ebafdf2dc 100644
> > --- a/gcc/config/i386/i386.h
> > +++ b/gcc/config/i386/i386.h
> > @@ -2341,7 +2341,7 @@ constexpr wide_int_bitmask PTA_ALDERLAKE =
> PTA_TREMONT | PTA_ADX | PTA_AVX
> >    | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ |
> PTA_SERIALIZE
> >    | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;  constexpr
> > wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
> > -  | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD;
> > +  | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD |
> PTA_ENQCMD |
> > + PTA_UINTR;
> >  constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS
> | PTA_AMX_FP16
> >    | PTA_PREFETCHI | PTA_AMX_COMPLEX;
> >  constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST |
> > PTA_RAOINT; diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index 26bcbe26c6c..dc385c1a3d8 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -32559,7 +32559,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES,
> PREFETCHW,
> > PCLMUL, RDRND, XSAVE, XSAVEC,  XSAVES, XSAVEOPT, FSGSBASE, PTWRITE,
> > RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,  MOVDIR64B, CLDEMOTE,
> WAITPKG,
> > ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,  PCONFIG, PKU, VAES,
> > VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -AVXIFMA,
> AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support.
> > +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and
> UINTR
> > +instruction set support.
> >
> >  @item grandridge
> >  Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> > SSE3, @@ -32567,8 +32568,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES,
> > PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,  XSAVES, XSAVEOPT,
> FSGSBASE,
> > PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,  MOVDIR64B,
> CLDEMOTE,
> > WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,  PCONFIG, PKU,
> > VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -AVXIFMA,
> > AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set -
> support.
> > +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD, UINTR
> and
> > +RAOINT instruction set support.
> >
> >  @item knl
> >  Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE,
> > SSE2, SSE3,
> > --
> > 2.25.1
> >
> 
> 
> --
> BR,
> Hongtao
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 5ac9c78d3ba..84ebafdf2dc 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2341,7 +2341,7 @@  constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX
   | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
   | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
 constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
-  | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD;
+  | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD | PTA_UINTR;
 constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
   | PTA_PREFETCHI | PTA_AMX_COMPLEX;
 constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT;
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 26bcbe26c6c..dc385c1a3d8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -32559,7 +32559,8 @@  SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
 XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
 MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
 PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support.
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction set
+support.
 
 @item grandridge
 Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
@@ -32567,8 +32568,8 @@  SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
 XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
 MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
 PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD and RAOINT instruction set
-support.
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD, UINTR and RAOINT
+instruction set support.
 
 @item knl
 Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,