diff mbox series

[v2,2/3] arm64: dts: marvell: Add NAND flash controller to AC5

Message ID 20230626031217.870938-3-chris.packham@alliedtelesis.co.nz
State New
Headers
Series mtd: rawnand: marvell: add support for AC5 SoC |

Commit Message

Chris Packham June 26, 2023, 3:12 a.m. UTC 
  The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to
the base SoC dtsi file as a disabled node. The NFC integration
on the AC5/AC5X only supports SDR timing modes up to 3 so requires a
dedicated compatible property so this limitation can be enforced.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---

Notes:
    Changes in v2:
    - New.

 arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Chris Packham June 30, 2023, 4:06 a.m. UTC | #1 
On 26/06/23 15:12, Chris Packham wrote:
> The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to
> the base SoC dtsi file as a disabled node. The NFC integration
> on the AC5/AC5X only supports SDR timing modes up to 3 so requires a
> dedicated compatible property so this limitation can be enforced.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>
> Notes:
>      Changes in v2:
>      - New.
>
>   arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 8bce64069138..74d644e0c29e 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -296,6 +296,16 @@ spi1: spi@805a8000 {
>   			status = "disabled";
>   		};
>   
> +		nand: nand-controller@805b0000 {
> +			compatible = "marvell,ac5-nand-controller";
> +			reg =  <0x0 0x805b0000 0x0 0x00000054>;
> +			#address-cells = <0x1>;
> +			#size-cells = <0x0>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cnm_clock>;

Actually I think I've just noticed a problem with this. The NFC uses a 
different clock not the cnm one. It's not a gating clock like other SoCs 
and they're close enough frequency wise so it mostly works. I'll update 
this to add a dedicated nand-clock for v3.

> +			status = "disabled";
> +		};
> +
>   		gic: interrupt-controller@80600000 {
>   			compatible = "arm,gic-v3";
>   			#interrupt-cells = <3>;
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 8bce64069138..74d644e0c29e 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -296,6 +296,16 @@  spi1: spi@805a8000 {
 			status = "disabled";
 		};
 
+		nand: nand-controller@805b0000 {
+			compatible = "marvell,ac5-nand-controller";
+			reg =  <0x0 0x805b0000 0x0 0x00000054>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cnm_clock>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@80600000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;