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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g2-20020aa7c582000000b0051d7fe0076bsi2968489edq.359.2023.06.26.10.15.50; Mon, 26 Jun 2023 10:16:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=mH7PKJVy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230005AbjFZQ5y (ORCPT <rfc822;filip.gregor98@gmail.com> + 99 others); Mon, 26 Jun 2023 12:57:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229457AbjFZQ5x (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 26 Jun 2023 12:57:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E669C4 for <linux-kernel@vger.kernel.org>; Mon, 26 Jun 2023 09:57:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7F21760EC7 for <linux-kernel@vger.kernel.org>; Mon, 26 Jun 2023 16:57:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4411AC433C8; Mon, 26 Jun 2023 16:57:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687798670; bh=D7OOp/89DCaiYbQMxKU0tOSDhjvcdtKgZcq1oLiZYw8=; h=From:To:Cc:Subject:Date:From; b=mH7PKJVyDXTVMM0pvqVTZGZvdM1pTfAZhbM2tmvYqv21ZLuWCizd5/AqVqL2/EY6i sFJYZoHET3zvjjKjCXV06M/ruxB21ID8bExYeIy75+ZTY2Frv30nCMAqU4wq8jTBzs lfc49vv+jxFKL4s0cr9XO5JWA+PyLk9E9uurc6k5RZKuyt05qEq2SobHhk051/mB0q q7gwjoJ2UXZc6A6RpUXHPJoZpj3oLfgFqy/tECf4oOrk4zIrRqpWKISigmCKlc8LmI E2klUHvloTfAnOQHCbbUkdsjQP5yqf5gx0eGloy2PVLHQTjFc0sglpyFXTiaupH3Sj GGPSInHOFd0MQ== From: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org Cc: =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>, linux-kernel@vger.kernel.org, linux@rivosinc.com, Palmer Dabbelt <palmer@rivosinc.com>, =?utf-8?q?R=C3=A9mi_Denis-Courmont?= <remi@remlab.net>, Darius Rad <darius@bluespec.com>, Andy Chiu <andy.chiu@sifive.com> Subject: [PATCH v2] riscv: Discard vector state on syscalls Date: Mon, 26 Jun 2023 18:57:36 +0200 Message-Id: <20230626165736.65927-1-bjorn@kernel.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769427069733835730?= X-GMAIL-MSGID: =?utf-8?q?1769786338776372999?= |
Series |
[v2] riscv: Discard vector state on syscalls
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Commit Message
Björn Töpel
June 26, 2023, 4:57 p.m. UTC
From: Björn Töpel <bjorn@rivosinc.com> The RISC-V vector specification states: Executing a system call causes all caller-saved vector registers (v0-v31, vl, vtype) and vstart to become unspecified. The vector registers are set to all 1s, vill is set (invalid), and the vector status is set to Initial. That way we can prevent userspace from accidentally relying on the stated save. Rémi pointed out [1] that writing to the registers might be superfluous, and setting vill is sufficient. Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] Suggested-by: Darius Rad <darius@bluespec.com> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> Suggested-by: Rémi Denis-Courmont <remi@remlab.net> Signed-off-by: Björn Töpel <bjorn@rivosinc.com> --- v1->v2: Proper register restore for initial state (Andy) Set registers to 1s, and not 0s (Darius) --- arch/riscv/include/asm/vector.h | 42 ++++++++++++++++++++++++++++++--- arch/riscv/kernel/traps.c | 2 ++ 2 files changed, 41 insertions(+), 3 deletions(-) base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3
Comments
Björn Töpel <bjorn@kernel.org> writes: > From: Björn Töpel <bjorn@rivosinc.com> > > The RISC-V vector specification states: > Executing a system call causes all caller-saved vector registers > (v0-v31, vl, vtype) and vstart to become unspecified. A bit of a corner case, but this will make sigreturn syscalls discard the vector state as well. Is that an issue? E.g. a user cannot build userspace context switching application. Does arm64 SVE handle sigreturn in a special way? Björn
Björn Töpel <bjorn@kernel.org> writes: > Björn Töpel <bjorn@kernel.org> writes: > >> From: Björn Töpel <bjorn@rivosinc.com> >> >> The RISC-V vector specification states: >> Executing a system call causes all caller-saved vector registers >> (v0-v31, vl, vtype) and vstart to become unspecified. > > A bit of a corner case, but this will make sigreturn syscalls discard > the vector state as well. > > Is that an issue? E.g. a user cannot build userspace context switching > application. Does arm64 SVE handle sigreturn in a special way? NVM; My bad. The vector state is cleared on *entry*, but then the registers passed on signal stack is restored as usual. Sorry for the noise! We're all good! Björn
On Tue, Jun 27, 2023 at 12:57 AM Björn Töpel <bjorn@kernel.org> wrote: > > From: Björn Töpel <bjorn@rivosinc.com> > > The RISC-V vector specification states: > Executing a system call causes all caller-saved vector registers > (v0-v31, vl, vtype) and vstart to become unspecified. > > The vector registers are set to all 1s, vill is set (invalid), and the > vector status is set to Initial. > > That way we can prevent userspace from accidentally relying on the > stated save. > > Rémi pointed out [1] that writing to the registers might be > superfluous, and setting vill is sufficient. > > Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] > Suggested-by: Darius Rad <darius@bluespec.com> > Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> > Suggested-by: Rémi Denis-Courmont <remi@remlab.net> > Signed-off-by: Björn Töpel <bjorn@rivosinc.com> > --- > v1->v2: > Proper register restore for initial state (Andy) > Set registers to 1s, and not 0s (Darius) > --- > arch/riscv/include/asm/vector.h | 42 ++++++++++++++++++++++++++++++--- > arch/riscv/kernel/traps.c | 2 ++ > 2 files changed, 41 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > index 04c0b07bf6cd..93d702d9988c 100644 > --- a/arch/riscv/include/asm/vector.h > +++ b/arch/riscv/include/asm/vector.h > @@ -139,14 +139,49 @@ static inline void riscv_v_vstate_save(struct task_struct *task, > } > } > > +static inline void __riscv_v_vstate_discard(void) > +{ > + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); > + > + riscv_v_enable(); > + asm volatile ( > + ".option push\n\t" > + ".option arch, +v\n\t" > + "vsetvli %0, x0, e8, m8, ta, ma\n\t" > + "vmv.v.i v0, -1\n\t" > + "vmv.v.i v8, -1\n\t" > + "vmv.v.i v16, -1\n\t" > + "vmv.v.i v24, -1\n\t" > + "vsetvl %0, x0, %1\n\t" > + ".option pop\n\t" > + : "=&r" (vl) : "r" (vtype_inval) : "memory"); > + riscv_v_disable(); > +} > + > +static inline void riscv_v_vstate_discard(struct pt_regs *regs) > +{ > + if (!riscv_v_vstate_query(regs)) > + return; > + > + __riscv_v_vstate_discard(); > + riscv_v_vstate_on(regs); > +} > + > static inline void riscv_v_vstate_restore(struct task_struct *task, > struct pt_regs *regs) > { > - if ((regs->status & SR_VS) != SR_VS_OFF) { > - struct __riscv_v_ext_state *vstate = &task->thread.vstate; > - > + struct __riscv_v_ext_state *vstate = &task->thread.vstate; > + unsigned long status = regs->status & SR_VS; > + > + switch (status) { > + case SR_VS_INITIAL: > + __riscv_v_vstate_discard(); > + break; > + case SR_VS_CLEAN: > + case SR_VS_DIRTY: > __riscv_v_vstate_restore(vstate, vstate->datap); > __riscv_v_vstate_clean(regs); > + break; > } > } > > @@ -178,6 +213,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } > #define __switch_to_vector(__prev, __next) do {} while (0) > #define riscv_v_vstate_off(regs) do {} while (0) > #define riscv_v_vstate_on(regs) do {} while (0) > +#define riscv_v_vstate_discard(regs) do {} while (0) > > #endif /* CONFIG_RISCV_ISA_V */ > > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c > index 5158961ea977..5ff63a784a6d 100644 > --- a/arch/riscv/kernel/traps.c > +++ b/arch/riscv/kernel/traps.c > @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) > regs->epc += 4; > regs->orig_a0 = regs->a0; > > + riscv_v_vstate_discard(regs); > + > syscall = syscall_enter_from_user_mode(regs, syscall); > > if (syscall < NR_syscalls) > > base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 > -- > 2.39.2 > Hi, the above part looks good to me. In the context of kernel-mode vector, it would also be good to just discard V-context at the syscall entry. So the kernel can freely use Vector if needed. I will rebase my work on top of yours. Another part that just came into my mind is the one for ptrace. Do we need to disallow, or immediately return all -1 if the tracee process is in the syscall path? It seems that we are likely to get stale values on datap if a tracee is being traced during a syscall. Thanks, Andy
Andy Chiu <andy.chiu@sifive.com> writes: > On Tue, Jun 27, 2023 at 12:57 AM Björn Töpel <bjorn@kernel.org> wrote: >> >> From: Björn Töpel <bjorn@rivosinc.com> >> >> The RISC-V vector specification states: >> Executing a system call causes all caller-saved vector registers >> (v0-v31, vl, vtype) and vstart to become unspecified. >> >> The vector registers are set to all 1s, vill is set (invalid), and the >> vector status is set to Initial. >> >> That way we can prevent userspace from accidentally relying on the >> stated save. >> >> Rémi pointed out [1] that writing to the registers might be >> superfluous, and setting vill is sufficient. >> >> Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] >> Suggested-by: Darius Rad <darius@bluespec.com> >> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> >> Suggested-by: Rémi Denis-Courmont <remi@remlab.net> >> Signed-off-by: Björn Töpel <bjorn@rivosinc.com> >> --- >> v1->v2: >> Proper register restore for initial state (Andy) >> Set registers to 1s, and not 0s (Darius) >> --- >> arch/riscv/include/asm/vector.h | 42 ++++++++++++++++++++++++++++++--- >> arch/riscv/kernel/traps.c | 2 ++ >> 2 files changed, 41 insertions(+), 3 deletions(-) >> >> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h >> index 04c0b07bf6cd..93d702d9988c 100644 >> --- a/arch/riscv/include/asm/vector.h >> +++ b/arch/riscv/include/asm/vector.h >> @@ -139,14 +139,49 @@ static inline void riscv_v_vstate_save(struct task_struct *task, >> } >> } >> >> +static inline void __riscv_v_vstate_discard(void) >> +{ >> + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); >> + >> + riscv_v_enable(); >> + asm volatile ( >> + ".option push\n\t" >> + ".option arch, +v\n\t" >> + "vsetvli %0, x0, e8, m8, ta, ma\n\t" >> + "vmv.v.i v0, -1\n\t" >> + "vmv.v.i v8, -1\n\t" >> + "vmv.v.i v16, -1\n\t" >> + "vmv.v.i v24, -1\n\t" >> + "vsetvl %0, x0, %1\n\t" >> + ".option pop\n\t" >> + : "=&r" (vl) : "r" (vtype_inval) : "memory"); >> + riscv_v_disable(); >> +} >> + >> +static inline void riscv_v_vstate_discard(struct pt_regs *regs) >> +{ >> + if (!riscv_v_vstate_query(regs)) >> + return; >> + >> + __riscv_v_vstate_discard(); >> + riscv_v_vstate_on(regs); >> +} >> + >> static inline void riscv_v_vstate_restore(struct task_struct *task, >> struct pt_regs *regs) >> { >> - if ((regs->status & SR_VS) != SR_VS_OFF) { >> - struct __riscv_v_ext_state *vstate = &task->thread.vstate; >> - >> + struct __riscv_v_ext_state *vstate = &task->thread.vstate; >> + unsigned long status = regs->status & SR_VS; >> + >> + switch (status) { >> + case SR_VS_INITIAL: >> + __riscv_v_vstate_discard(); >> + break; >> + case SR_VS_CLEAN: >> + case SR_VS_DIRTY: >> __riscv_v_vstate_restore(vstate, vstate->datap); >> __riscv_v_vstate_clean(regs); >> + break; >> } >> } >> >> @@ -178,6 +213,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } >> #define __switch_to_vector(__prev, __next) do {} while (0) >> #define riscv_v_vstate_off(regs) do {} while (0) >> #define riscv_v_vstate_on(regs) do {} while (0) >> +#define riscv_v_vstate_discard(regs) do {} while (0) >> >> #endif /* CONFIG_RISCV_ISA_V */ >> >> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c >> index 5158961ea977..5ff63a784a6d 100644 >> --- a/arch/riscv/kernel/traps.c >> +++ b/arch/riscv/kernel/traps.c >> @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) >> regs->epc += 4; >> regs->orig_a0 = regs->a0; >> >> + riscv_v_vstate_discard(regs); >> + >> syscall = syscall_enter_from_user_mode(regs, syscall); >> >> if (syscall < NR_syscalls) >> >> base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 >> -- >> 2.39.2 >> > > Hi, the above part looks good to me. In the context of kernel-mode > vector, it would also be good to just discard V-context at the syscall > entry. So the kernel can freely use Vector if needed. I will rebase my > work on top of yours. Ok! > Another part that just came into my mind is the one for ptrace. Do we > need to disallow, or immediately return all -1 if the tracee process > is in the syscall path? It seems that we are likely to get stale > values on datap if a tracee is being traced during a syscall. Hmm, could you elaborate a bit on when the tracer would get stale regs?
On Wed, Jun 28, 2023 at 6:35 PM Björn Töpel <bjorn@kernel.org> wrote: > > Andy Chiu <andy.chiu@sifive.com> writes: > > > On Tue, Jun 27, 2023 at 12:57 AM Björn Töpel <bjorn@kernel.org> wrote: > >> > >> From: Björn Töpel <bjorn@rivosinc.com> > >> > >> The RISC-V vector specification states: > >> Executing a system call causes all caller-saved vector registers > >> (v0-v31, vl, vtype) and vstart to become unspecified. > >> > >> The vector registers are set to all 1s, vill is set (invalid), and the > >> vector status is set to Initial. > >> > >> That way we can prevent userspace from accidentally relying on the > >> stated save. > >> > >> Rémi pointed out [1] that writing to the registers might be > >> superfluous, and setting vill is sufficient. > >> > >> Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] > >> Suggested-by: Darius Rad <darius@bluespec.com> > >> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> > >> Suggested-by: Rémi Denis-Courmont <remi@remlab.net> > >> Signed-off-by: Björn Töpel <bjorn@rivosinc.com> > >> --- > >> v1->v2: > >> Proper register restore for initial state (Andy) > >> Set registers to 1s, and not 0s (Darius) > >> --- > >> arch/riscv/include/asm/vector.h | 42 ++++++++++++++++++++++++++++++--- > >> arch/riscv/kernel/traps.c | 2 ++ > >> 2 files changed, 41 insertions(+), 3 deletions(-) > >> > >> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > >> index 04c0b07bf6cd..93d702d9988c 100644 > >> --- a/arch/riscv/include/asm/vector.h > >> +++ b/arch/riscv/include/asm/vector.h > >> @@ -139,14 +139,49 @@ static inline void riscv_v_vstate_save(struct task_struct *task, > >> } > >> } > >> > >> +static inline void __riscv_v_vstate_discard(void) > >> +{ > >> + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); > >> + > >> + riscv_v_enable(); > >> + asm volatile ( > >> + ".option push\n\t" > >> + ".option arch, +v\n\t" > >> + "vsetvli %0, x0, e8, m8, ta, ma\n\t" > >> + "vmv.v.i v0, -1\n\t" > >> + "vmv.v.i v8, -1\n\t" > >> + "vmv.v.i v16, -1\n\t" > >> + "vmv.v.i v24, -1\n\t" > >> + "vsetvl %0, x0, %1\n\t" > >> + ".option pop\n\t" > >> + : "=&r" (vl) : "r" (vtype_inval) : "memory"); > >> + riscv_v_disable(); > >> +} > >> + > >> +static inline void riscv_v_vstate_discard(struct pt_regs *regs) > >> +{ > >> + if (!riscv_v_vstate_query(regs)) > >> + return; > >> + > >> + __riscv_v_vstate_discard(); > >> + riscv_v_vstate_on(regs); > >> +} > >> + > >> static inline void riscv_v_vstate_restore(struct task_struct *task, > >> struct pt_regs *regs) > >> { > >> - if ((regs->status & SR_VS) != SR_VS_OFF) { > >> - struct __riscv_v_ext_state *vstate = &task->thread.vstate; > >> - > >> + struct __riscv_v_ext_state *vstate = &task->thread.vstate; > >> + unsigned long status = regs->status & SR_VS; > >> + > >> + switch (status) { > >> + case SR_VS_INITIAL: > >> + __riscv_v_vstate_discard(); > >> + break; > >> + case SR_VS_CLEAN: > >> + case SR_VS_DIRTY: > >> __riscv_v_vstate_restore(vstate, vstate->datap); > >> __riscv_v_vstate_clean(regs); > >> + break; > >> } > >> } > >> > >> @@ -178,6 +213,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } > >> #define __switch_to_vector(__prev, __next) do {} while (0) > >> #define riscv_v_vstate_off(regs) do {} while (0) > >> #define riscv_v_vstate_on(regs) do {} while (0) > >> +#define riscv_v_vstate_discard(regs) do {} while (0) > >> > >> #endif /* CONFIG_RISCV_ISA_V */ > >> > >> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c > >> index 5158961ea977..5ff63a784a6d 100644 > >> --- a/arch/riscv/kernel/traps.c > >> +++ b/arch/riscv/kernel/traps.c > >> @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) > >> regs->epc += 4; > >> regs->orig_a0 = regs->a0; > >> > >> + riscv_v_vstate_discard(regs); > >> + > >> syscall = syscall_enter_from_user_mode(regs, syscall); > >> > >> if (syscall < NR_syscalls) > >> > >> base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 > >> -- > >> 2.39.2 > >> > > > > Hi, the above part looks good to me. In the context of kernel-mode > > vector, it would also be good to just discard V-context at the syscall > > entry. So the kernel can freely use Vector if needed. I will rebase my > > work on top of yours. > > Ok! > > > Another part that just came into my mind is the one for ptrace. Do we > > need to disallow, or immediately return all -1 if the tracee process > > is in the syscall path? It seems that we are likely to get stale > > values on datap if a tracee is being traced during a syscall. > > Hmm, could you elaborate a bit on when the tracer would get stale regs? Yep, consider that our tracer process attaches to a tracee with PTRACE_SYSCALL. Then, the tracee will let the tracer to inspect it whenever it makes a syscall. The tracer wants to inspect V-registers at these PTRACE_SYSCALL stops. Assume the tracee context switches out before being inspected (Sadly I didn't find this part in the code, so maybe I was wrong). Now, we set all V-regs to -1 and VS to 'On' entering a syscall. However, -1 will not be saved into datap, which the tracer copies from, because riscv_v_vstate_save() only saves whenever VS is 'Dirty'. We intentionally want this because it saves unnecessary context saves. As a result, what we will get with REGSET_V will not reflect the latest one, and what we set will get lost since VS='ON' restores V to -1. Since we are planning to discard V registers on syscall, does it make sense to also make ptrace aware of this? Or, just leave it as-it because reading/writing V register at syscall is not meaningful already. Thanks, Andy
Andy Chiu <andy.chiu@sifive.com> writes: > On Wed, Jun 28, 2023 at 6:35 PM Björn Töpel <bjorn@kernel.org> wrote: >> >> Andy Chiu <andy.chiu@sifive.com> writes: >> >> > On Tue, Jun 27, 2023 at 12:57 AM Björn Töpel <bjorn@kernel.org> wrote: >> >> >> >> From: Björn Töpel <bjorn@rivosinc.com> >> >> >> >> The RISC-V vector specification states: >> >> Executing a system call causes all caller-saved vector registers >> >> (v0-v31, vl, vtype) and vstart to become unspecified. >> >> >> >> The vector registers are set to all 1s, vill is set (invalid), and the >> >> vector status is set to Initial. >> >> >> >> That way we can prevent userspace from accidentally relying on the >> >> stated save. >> >> >> >> Rémi pointed out [1] that writing to the registers might be >> >> superfluous, and setting vill is sufficient. >> >> >> >> Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1] >> >> Suggested-by: Darius Rad <darius@bluespec.com> >> >> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com> >> >> Suggested-by: Rémi Denis-Courmont <remi@remlab.net> >> >> Signed-off-by: Björn Töpel <bjorn@rivosinc.com> >> >> --- >> >> v1->v2: >> >> Proper register restore for initial state (Andy) >> >> Set registers to 1s, and not 0s (Darius) >> >> --- >> >> arch/riscv/include/asm/vector.h | 42 ++++++++++++++++++++++++++++++--- >> >> arch/riscv/kernel/traps.c | 2 ++ >> >> 2 files changed, 41 insertions(+), 3 deletions(-) >> >> >> >> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h >> >> index 04c0b07bf6cd..93d702d9988c 100644 >> >> --- a/arch/riscv/include/asm/vector.h >> >> +++ b/arch/riscv/include/asm/vector.h >> >> @@ -139,14 +139,49 @@ static inline void riscv_v_vstate_save(struct task_struct *task, >> >> } >> >> } >> >> >> >> +static inline void __riscv_v_vstate_discard(void) >> >> +{ >> >> + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); >> >> + >> >> + riscv_v_enable(); >> >> + asm volatile ( >> >> + ".option push\n\t" >> >> + ".option arch, +v\n\t" >> >> + "vsetvli %0, x0, e8, m8, ta, ma\n\t" >> >> + "vmv.v.i v0, -1\n\t" >> >> + "vmv.v.i v8, -1\n\t" >> >> + "vmv.v.i v16, -1\n\t" >> >> + "vmv.v.i v24, -1\n\t" >> >> + "vsetvl %0, x0, %1\n\t" >> >> + ".option pop\n\t" >> >> + : "=&r" (vl) : "r" (vtype_inval) : "memory"); >> >> + riscv_v_disable(); >> >> +} >> >> + >> >> +static inline void riscv_v_vstate_discard(struct pt_regs *regs) >> >> +{ >> >> + if (!riscv_v_vstate_query(regs)) >> >> + return; >> >> + >> >> + __riscv_v_vstate_discard(); >> >> + riscv_v_vstate_on(regs); >> >> +} >> >> + >> >> static inline void riscv_v_vstate_restore(struct task_struct *task, >> >> struct pt_regs *regs) >> >> { >> >> - if ((regs->status & SR_VS) != SR_VS_OFF) { >> >> - struct __riscv_v_ext_state *vstate = &task->thread.vstate; >> >> - >> >> + struct __riscv_v_ext_state *vstate = &task->thread.vstate; >> >> + unsigned long status = regs->status & SR_VS; >> >> + >> >> + switch (status) { >> >> + case SR_VS_INITIAL: >> >> + __riscv_v_vstate_discard(); >> >> + break; >> >> + case SR_VS_CLEAN: >> >> + case SR_VS_DIRTY: >> >> __riscv_v_vstate_restore(vstate, vstate->datap); >> >> __riscv_v_vstate_clean(regs); >> >> + break; >> >> } >> >> } >> >> >> >> @@ -178,6 +213,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } >> >> #define __switch_to_vector(__prev, __next) do {} while (0) >> >> #define riscv_v_vstate_off(regs) do {} while (0) >> >> #define riscv_v_vstate_on(regs) do {} while (0) >> >> +#define riscv_v_vstate_discard(regs) do {} while (0) >> >> >> >> #endif /* CONFIG_RISCV_ISA_V */ >> >> >> >> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c >> >> index 5158961ea977..5ff63a784a6d 100644 >> >> --- a/arch/riscv/kernel/traps.c >> >> +++ b/arch/riscv/kernel/traps.c >> >> @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) >> >> regs->epc += 4; >> >> regs->orig_a0 = regs->a0; >> >> >> >> + riscv_v_vstate_discard(regs); >> >> + >> >> syscall = syscall_enter_from_user_mode(regs, syscall); >> >> >> >> if (syscall < NR_syscalls) >> >> >> >> base-commit: 488833ccdcac118da16701f4ee0673b20ba47fe3 >> >> -- >> >> 2.39.2 >> >> >> > >> > Hi, the above part looks good to me. In the context of kernel-mode >> > vector, it would also be good to just discard V-context at the syscall >> > entry. So the kernel can freely use Vector if needed. I will rebase my >> > work on top of yours. >> >> Ok! >> >> > Another part that just came into my mind is the one for ptrace. Do we >> > need to disallow, or immediately return all -1 if the tracee process >> > is in the syscall path? It seems that we are likely to get stale >> > values on datap if a tracee is being traced during a syscall. >> >> Hmm, could you elaborate a bit on when the tracer would get stale regs? > > Yep, consider that our tracer process attaches to a tracee with > PTRACE_SYSCALL. Then, the tracee will let the tracer to inspect it > whenever it makes a syscall. The tracer wants to inspect V-registers > at these PTRACE_SYSCALL stops. Assume the tracee context switches out > before being inspected (Sadly I didn't find this part in the code, so > maybe I was wrong). Now, we set all V-regs to -1 and VS to 'On' > entering a syscall. However, -1 will not be saved into datap, which > the tracer copies from, because riscv_v_vstate_save() only saves > whenever VS is 'Dirty'. We intentionally want this because it saves > unnecessary context saves. As a result, what we will get with REGSET_V > will not reflect the latest one, and what we set will get lost since > VS='ON' restores V to -1. It's not a racy, but you're correct that setting the state to Initial, will cause issues. When get/set_regs is called, the tracee will be stopped, and a schedule() has been done. Tracee: syscall-->(datap stale; change dirty->initial)-->stopped (datap still stale). Tracer will get stale data. > Since we are planning to discard V registers on syscall, does it make > sense to also make ptrace aware of this? Or, just leave it as-it > because reading/writing V register at syscall is not meaningful > already. Special handling for ptrace is a bit overkill -- at least now. I'll spin a v3, where discard simply sets the state to dirty. Thanks for finding this! Björn
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 04c0b07bf6cd..93d702d9988c 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -139,14 +139,49 @@ static inline void riscv_v_vstate_save(struct task_struct *task, } } +static inline void __riscv_v_vstate_discard(void) +{ + unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1); + + riscv_v_enable(); + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vmv.v.i v0, -1\n\t" + "vmv.v.i v8, -1\n\t" + "vmv.v.i v16, -1\n\t" + "vmv.v.i v24, -1\n\t" + "vsetvl %0, x0, %1\n\t" + ".option pop\n\t" + : "=&r" (vl) : "r" (vtype_inval) : "memory"); + riscv_v_disable(); +} + +static inline void riscv_v_vstate_discard(struct pt_regs *regs) +{ + if (!riscv_v_vstate_query(regs)) + return; + + __riscv_v_vstate_discard(); + riscv_v_vstate_on(regs); +} + static inline void riscv_v_vstate_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) != SR_VS_OFF) { - struct __riscv_v_ext_state *vstate = &task->thread.vstate; - + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + unsigned long status = regs->status & SR_VS; + + switch (status) { + case SR_VS_INITIAL: + __riscv_v_vstate_discard(); + break; + case SR_VS_CLEAN: + case SR_VS_DIRTY: __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); + break; } } @@ -178,6 +213,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) +#define riscv_v_vstate_discard(regs) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 5158961ea977..5ff63a784a6d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -296,6 +296,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) regs->epc += 4; regs->orig_a0 = regs->a0; + riscv_v_vstate_discard(regs); + syscall = syscall_enter_from_user_mode(regs, syscall); if (syscall < NR_syscalls)