Message ID | 20230624-sm6125-dpu-v1-13-1d5a638cebf2@somainline.org |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6126834vqr; Fri, 23 Jun 2023 17:43:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6A/jyNXYWE7F4k/5pXdGf6b1qyP/GerxYAb9pyj9u7ZOyUEtucGd4kZr4wu3VHBZryxx2K X-Received: by 2002:a92:c70f:0:b0:33e:5ea2:bd00 with SMTP id a15-20020a92c70f000000b0033e5ea2bd00mr13665364ilp.17.1687567405692; Fri, 23 Jun 2023 17:43:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687567405; cv=none; d=google.com; s=arc-20160816; b=nXmqGG3tITBSeeY9FDROn7nDQIEKjKqL4vwBHyqMjVG87vkIff0YcJORn/cTcZ+8wA CVMbNFzuhsUDpzo3N2oVDO61rbkCSiP3hJrBgZmFshHiLWiJKicP8S6mDK1/NZpoXqLL hHt2clCNZAhbQNSQHTl9CUd6mduwkjlUdUTwjIahVU2dQB5NK2qEfnCDI48qS8Narm8l rg4NBkY1PuLgT3dRfoh1Eu/Pb/rNJ8w4oYu/bOS5SrMHk9r/Mfn9O1C2Y+zQ/KCVOSJw K/mVJFtvdN40mOjIseSZXs4g3SQR0N2nkhpJHi2LzFyBK3/uxsKxTYfpZoGcd0I3FjfF NUJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=91ioSvOTk5D8RVdD5K4SOBeMnC3zPUUI4RZzWF2a7C8=; fh=OfzUp+OcwbFUfZC2mGhS6GGXsXqM7NhjMWKyOt4HPQU=; b=Bgcg6x1MXstSu6KwrDSRhQgFzrqQk3ICyDLVJu9GuxnjNJbeTYLSfuvzTQlNvhOpjX noRh0y53qYqyCQ2jgwCgl3YiC9+cTpMAcUFOK+pZaFg+bcIty5fVMRPzv+UYbGpYdbbS ImSiD2s41uxSic8oo181VnKqFCe8X8YIjeWzEoi4caDn5AfQvWr1B+GXWRpXY6oL5Kv2 bE+QuvPg48POkdbpYAL+VEZxflyGzB9dQ8jBXEEGBAzA6UpuWv4d2vLimsJ4PUF31rKm Me57Ncfd4/eOUaXAgKxFvaPhJFyi8xXUJQJUkgozVaG4UIcvB/g2fCYmlS+CW9P2LwBh j3cg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w191-20020a6382c8000000b00530b3b98fc5si531926pgd.417.2023.06.23.17.43.13; Fri, 23 Jun 2023 17:43:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232603AbjFXAmM (ORCPT <rfc822;maxin.john@gmail.com> + 99 others); Fri, 23 Jun 2023 20:42:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232276AbjFXAlb (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 23 Jun 2023 20:41:31 -0400 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F3BE2957 for <linux-kernel@vger.kernel.org>; Fri, 23 Jun 2023 17:41:19 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id AF3003F858; Sat, 24 Jun 2023 02:41:16 +0200 (CEST) From: Marijn Suijten <marijn.suijten@somainline.org> Date: Sat, 24 Jun 2023 02:41:11 +0200 Subject: [PATCH 13/15] arm64: dts: qcom: sm6125: Add dispcc node MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230624-sm6125-dpu-v1-13-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Krishna Manikandan <quic_mkrishn@quicinc.com> Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Konrad Dybcio <konrad.dybcio@linaro.org>, Martin Botka <martin.botka@somainline.org>, Jami Kettunen <jami.kettunen@somainline.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Lux Aliaga <they@mint.lgbt>, Marijn Suijten <marijn.suijten@somainline.org> X-Mailer: b4 0.12.2 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769542679943078121?= X-GMAIL-MSGID: =?utf-8?q?1769542679943078121?= |
Series |
drm/msm: Add SM6125 MDSS/DPU hardware and enable Sony Xperia 10 II panel
|
|
Commit Message
Marijn Suijten
June 24, 2023, 12:41 a.m. UTC
Enable and configure the dispcc node on SM6125 for consumption by MDSS
later on.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
Comments
On 24.06.2023 02:41, Marijn Suijten wrote: > Enable and configure the dispcc node on SM6125 for consumption by MDSS > later on. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index edb03508dba3..7d78b4e48ebe 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > */ > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > @@ -1203,6 +1204,28 @@ sram@4690000 { > reg = <0x04690000 0x10000>; > }; > > + dispcc: clock-controller@5f00000 { > + compatible = "qcom,sm6125-dispcc"; > + reg = <0x05f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <0>, are you.. > + <0>, > + <0>, > + <0>, > + <0>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > + clock-names = "bi_tcxo", > + "gcc_disp_gpll0_div_clk_src", ..sure? Konrad > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk"; > + power-domains = <&rpmpd SM6125_VDDCX>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > apps_smmu: iommu@c600000 { > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0c600000 0x80000>; >
On 24/06/2023 03:41, Marijn Suijten wrote: > Enable and configure the dispcc node on SM6125 for consumption by MDSS > later on. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index edb03508dba3..7d78b4e48ebe 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > */ > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > @@ -1203,6 +1204,28 @@ sram@4690000 { > reg = <0x04690000 0x10000>; > }; > > + dispcc: clock-controller@5f00000 { > + compatible = "qcom,sm6125-dispcc"; > + reg = <0x05f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; This clock is at the wrong position. > + clock-names = "bi_tcxo", > + "gcc_disp_gpll0_div_clk_src", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk"; > + power-domains = <&rpmpd SM6125_VDDCX>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > apps_smmu: iommu@c600000 { > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x0c600000 0x80000>; >
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index edb03508dba3..7d78b4e48ebe 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> */ +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -1203,6 +1204,28 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; + dispcc: clock-controller@5f00000 { + compatible = "qcom,sm6125-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmpd SM6125_VDDCX>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>;