Message ID | 4f4136a91b24d3ad35fa12bd19fe14b83da9affe.1687414716.git.quic_varada@quicinc.com |
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Thu, 22 Jun 2023 06:22:46 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35M6Mjef022697 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Jun 2023 06:22:45 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 21 Jun 2023 23:22:38 -0700 From: Varadarajan Narayanan <quic_varada@quicinc.com> To: <agross@kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <vkoul@kernel.org>, <kishon@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <gregkh@linuxfoundation.org>, <catalin.marinas@arm.com>, <will@kernel.org>, <p.zabel@pengutronix.de>, <arnd@arndb.de>, <geert+renesas@glider.be>, <neil.armstrong@linaro.org>, <nfraprado@collabora.com>, <broonie@kernel.org>, <rafal@milecki.pl>, <quic_srichara@quicinc.com>, <quic_varada@quicinc.org>, <quic_wcheng@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-usb@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> CC: Varadarajan Narayanan <quic_varada@quicinc.com> Subject: [PATCH v2 2/6] dt-bindings: phy: qcom,m31: Document qcom,m31 USB phy Date: Thu, 22 Jun 2023 11:52:09 +0530 Message-ID: <4f4136a91b24d3ad35fa12bd19fe14b83da9affe.1687414716.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <cover.1687414716.git.quic_varada@quicinc.com> References: <cover.1687414716.git.quic_varada@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: W1qHr0IMF1HOcIe1O7rXysUae2QmRHKA X-Proofpoint-GUID: W1qHr0IMF1HOcIe1O7rXysUae2QmRHKA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_03,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220052 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769384494923211021?= X-GMAIL-MSGID: =?utf-8?q?1769384494923211021?= |
Series |
Enable IPQ5332 USB2
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Commit Message
Varadarajan Narayanan
June 22, 2023, 6:22 a.m. UTC
Document the M31 USB2 phy present in IPQ5332. Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- v1: Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml Drop default binding "m31,usb-hsphy" Add clock Remove 'oneOf' from compatible Remove 'qscratch' region from register space as it is not needed Remove reset-names Fix the example definition --- .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
Comments
On Thu, Jun 22, 2023 at 11:52:09AM +0530, Varadarajan Narayanan wrote: > Document the M31 USB2 phy present in IPQ5332. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v1: > Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml > Drop default binding "m31,usb-hsphy" > Add clock > Remove 'oneOf' from compatible > Remove 'qscratch' region from register space as it is not needed > Remove reset-names > Fix the example definition > --- > .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 51 ++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > new file mode 100644 > index 0000000..ab2e945 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: M31 (https://www.m31tech.com) USB PHY Put the URL in 'description'. > + > +maintainers: > + - Sricharan Ramabadhran <quic_srichara@quicinc.com> > + - Varadarajan Narayanan <quic_varada@quicinc.org> .org? It's .com everywhere else. > + > +description: > + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. Where's the IPQ5018 compatible? > + > +properties: > + compatible: > + items: > + - enum: > + - qcom,ipq5332-usb-hsphy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + maxItems: 1 > + contains: 'contains' is not appropriate here. Drop. > + items: > + - const: cfg_ahb Don't need both items list and maxItems. Really, you don't need 'clock-names' at all because there is only 1 clock. > + > + resets: > + maxItems: 1 > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > + usbphy0: ipq5332-hsphy@7b000 { Drop unused labels. > + compatible = "qcom,ipq5332-usb-hsphy"; > + reg = <0x0007b000 0x12c>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > + clock-names = "cfg_ahb"; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; Whitespace errors in here. > + }; > + > -- > 2.7.4 >
On Thu, Jun 22, 2023 at 08:46:27AM -0600, Rob Herring wrote: > On Thu, Jun 22, 2023 at 11:52:09AM +0530, Varadarajan Narayanan wrote: > > Document the M31 USB2 phy present in IPQ5332. > > > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > v1: > > Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml > > Drop default binding "m31,usb-hsphy" > > Add clock > > Remove 'oneOf' from compatible > > Remove 'qscratch' region from register space as it is not needed > > Remove reset-names > > Fix the example definition > > --- > > .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 51 ++++++++++++++++++++++ > > 1 file changed, 51 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > new file mode 100644 > > index 0000000..ab2e945 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > @@ -0,0 +1,51 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: M31 (https://www.m31tech.com) USB PHY > > Put the URL in 'description'. Ok. > > + > > +maintainers: > > + - Sricharan Ramabadhran <quic_srichara@quicinc.com> > > + - Varadarajan Narayanan <quic_varada@quicinc.org> > > .org? It's .com everywhere else. Ok. > > + > > +description: > > + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. > > Where's the IPQ5018 compatible? In the previous version had a default and IPQ5332 specific compatible. IPQ5018 would have used the default compatible. However, in the review was asked to drop the default compatible. Hence planned to include ipq5018 compatible and post it in separate patchset while enabling IPQ5018 USB. IPQ5018 init is also diffferent from the init used here. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - qcom,ipq5332-usb-hsphy > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + maxItems: 1 > > + contains: > > 'contains' is not appropriate here. Drop. > > > + items: > > + - const: cfg_ahb > > Don't need both items list and maxItems. Really, you don't need > 'clock-names' at all because there is only 1 clock. Will drop 'clock-names'. > > + > > + resets: > > + maxItems: 1 > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > > + usbphy0: ipq5332-hsphy@7b000 { > > Drop unused labels. Ok. > > + compatible = "qcom,ipq5332-usb-hsphy"; > > + reg = <0x0007b000 0x12c>; > > + > > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > > + clock-names = "cfg_ahb"; > > + > > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > Whitespace errors in here. Ok. Thanks Varada > > + }; > > + > > -- > > 2.7.4 > >
On 23/06/2023 07:45, Varadarajan Narayanan wrote: > >>> + >>> +description: >>> + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. >> >> Where's the IPQ5018 compatible? > > In the previous version had a default and IPQ5332 specific > compatible. IPQ5018 would have used the default compatible. > However, in the review was asked to drop the default compatible. > Hence planned to include ipq5018 compatible and post it in > separate patchset while enabling IPQ5018 USB. IPQ5018 init is > also diffferent from the init used here. Your previous patch did not have ipq5018 compatible. There was nothing indicating that some default means ipq5018... Best regards, Krzysztof
On 22/06/2023 08:22, Varadarajan Narayanan wrote: > Document the M31 USB2 phy present in IPQ5332. > > +description: > + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. > + > +properties: > + compatible: > + items: Also drop items. > + - enum: > + - qcom,ipq5332-usb-hsphy > + Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml new file mode 100644 index 0000000..ab2e945 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: M31 (https://www.m31tech.com) USB PHY + +maintainers: + - Sricharan Ramabadhran <quic_srichara@quicinc.com> + - Varadarajan Narayanan <quic_varada@quicinc.org> + +description: + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. + +properties: + compatible: + items: + - enum: + - qcom,ipq5332-usb-hsphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + contains: + items: + - const: cfg_ahb + + resets: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + usbphy0: ipq5332-hsphy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + clock-names = "cfg_ahb"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + }; +