[1/2] arm64: dts: qcom: sc8280xp: fix UFS reference clocks

Message ID 20221104092045.17410-2-johan+linaro@kernel.org
State New
Headers
Series arm64: dts: qcom: sc8280xp: fix UFS reference clocks and PHY nodes |

Commit Message

Johan Hovold Nov. 4, 2022, 9:20 a.m. UTC
  There are three UFS reference clocks on SC8280XP which are used as
follows:

 - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
   to either controller.

 - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
   provide reference clocks to the two PHYs.

Note that this depends on first updating the clock driver to reflect
that all three clocks are sourced from CXO. Specifically, the UFS
controller driver expects the device reference clock to have a valid
frequency:

	ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Fixes: 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")
Fixes: f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")
Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/
Cc: stable@vger.kernel.org	# 5.20
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
  

Comments

Konrad Dybcio Nov. 4, 2022, 9:43 a.m. UTC | #1
On 04/11/2022 10:20, Johan Hovold wrote:
> There are three UFS reference clocks on SC8280XP which are used as
> follows:
>
>   - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
>     to either controller.
>
>   - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
>     provide reference clocks to the two PHYs.
>
> Note that this depends on first updating the clock driver to reflect
> that all three clocks are sourced from CXO. Specifically, the UFS
> controller driver expects the device reference clock to have a valid
> frequency:
>
> 	ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Fixes: 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")
> Fixes: f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")
> Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/
> Cc: stable@vger.kernel.org	# 5.20
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>


Konrad

>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 21ac119e0382..e0d0fb6994b5 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -912,7 +912,7 @@ ufs_mem_hc: ufs@1d84000 {
>   				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>   				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>   				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> -				 <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
>   				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>   				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>   				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> @@ -943,7 +943,7 @@ ufs_mem_phy: phy@1d87000 {
>   			ranges;
>   			clock-names = "ref",
>   				      "ref_aux";
> -			clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
> +			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
>   				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
>   
>   			resets = <&ufs_mem_hc 0>;
> @@ -980,7 +980,7 @@ ufs_card_hc: ufs@1da4000 {
>   				 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
>   				 <&gcc GCC_UFS_CARD_AHB_CLK>,
>   				 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
> -				 <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
>   				 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
>   				 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
>   				 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
> @@ -1011,7 +1011,7 @@ ufs_card_phy: phy@1da7000 {
>   			ranges;
>   			clock-names = "ref",
>   				      "ref_aux";
> -			clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
> +			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
>   				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
>   
>   			resets = <&ufs_card_hc 0>;
  
Brian Masney Nov. 7, 2022, 11:09 a.m. UTC | #2
On Fri, Nov 04, 2022 at 10:20:44AM +0100, Johan Hovold wrote:
> There are three UFS reference clocks on SC8280XP which are used as
> follows:
> 
>  - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
>    to either controller.
> 
>  - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
>    provide reference clocks to the two PHYs.
> 
> Note that this depends on first updating the clock driver to reflect
> that all three clocks are sourced from CXO. Specifically, the UFS
> controller driver expects the device reference clock to have a valid
> frequency:
> 
> 	ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0
> 
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Fixes: 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")
> Fixes: f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")
> Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/
> Cc: stable@vger.kernel.org	# 5.20
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Reviewed-by: Brian Masney <bmasney@redhat.com>

Note that there was no 5.20 kernel; that should be 6.0. Bjorn should be
able to fix this up during merge.

https://en.wikipedia.org/wiki/Linux_kernel_version_history
  
Johan Hovold Nov. 7, 2022, 12:23 p.m. UTC | #3
On Mon, Nov 07, 2022 at 06:09:12AM -0500, Brian Masney wrote:
> On Fri, Nov 04, 2022 at 10:20:44AM +0100, Johan Hovold wrote:
> > There are three UFS reference clocks on SC8280XP which are used as
> > follows:
> > 
> >  - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
> >    to either controller.
> > 
> >  - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
> >    provide reference clocks to the two PHYs.
> > 
> > Note that this depends on first updating the clock driver to reflect
> > that all three clocks are sourced from CXO. Specifically, the UFS
> > controller driver expects the device reference clock to have a valid
> > frequency:
> > 
> > 	ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0
> > 
> > Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> > Fixes: 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")
> > Fixes: f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")
> > Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/
> > Cc: stable@vger.kernel.org	# 5.20
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> 
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> 
> Note that there was no 5.20 kernel; that should be 6.0. Bjorn should be
> able to fix this up during merge.

Good catch. I based this on a tag created before 6.0 was released and
failed to notice.

Johan
  

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 21ac119e0382..e0d0fb6994b5 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -912,7 +912,7 @@  ufs_mem_hc: ufs@1d84000 {
 				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 				 <&gcc GCC_UFS_PHY_AHB_CLK>,
 				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
-				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
 				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
@@ -943,7 +943,7 @@  ufs_mem_phy: phy@1d87000 {
 			ranges;
 			clock-names = "ref",
 				      "ref_aux";
-			clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
+			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
 				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 
 			resets = <&ufs_mem_hc 0>;
@@ -980,7 +980,7 @@  ufs_card_hc: ufs@1da4000 {
 				 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
 				 <&gcc GCC_UFS_CARD_AHB_CLK>,
 				 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
-				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
 				 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
 				 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
 				 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
@@ -1011,7 +1011,7 @@  ufs_card_phy: phy@1da7000 {
 			ranges;
 			clock-names = "ref",
 				      "ref_aux";
-			clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
+			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
 				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
 
 			resets = <&ufs_card_hc 0>;