[v3] arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain
Commit Message
CAN instances 3 and 5 in the main domain are brought on the common
processor board through header J27 and J28. The CAN High and Low lines
from the SoC are routed through a mux on the SoM. The select lines need
to be set for the CAN signals to get connected to the transceivers on
the common processor board. Threfore, add respective mux, transceiver
dt nodes to add support for these CAN instances.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
---
Changelog v2->v3: Removed tiL6.1 subject prefix
Link to v2 : https://lore.kernel.org/all/20230523085021.22524-1-b-kapoor@ti.com/
.../dts/ti/k3-j721s2-common-proc-board.dts | 46 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 12 +++++
2 files changed, 58 insertions(+)
Comments
Hi Bhavya,
> [...]
>+ mux0: mux-controller0 {
>+ compatible = "gpio-mux";
>+ #mux-state-cells = <1>;
>+ mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
>+ };
>+
>+ mux1: mux-controller1 {
>+ compatible = "gpio-mux";
>+ #mux-state-cells = <1>;
>+ mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
>+ };
>+
/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dtb: mux-controller0: $nodename:0: 'mux-controller0' does not match '^mux-controller(@.*|-[0-9a-f]+)?$'
Documentation/devicetree/bindings/mux/mux-controller.yaml
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dtb: mux-controller1: $nodename:0: 'mux-controller1' does not match '^mux-controller(@.*|-[0-9a-f]+)?$'
Please fix above dtbs_check warning
For rest
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
> transceiver0: can-phy0 {
> /* standby pin has been grounded by default */
> compatible = "ti,tcan1042";
>--
>2.39.2
@@ -27,6 +27,8 @@ aliases {
can0 = &main_mcan16;
can1 = &mcu_mcan0;
can2 = &mcu_mcan1;
+ can3 = &main_mcan3;
+ can4 = &main_mcan5;
};
evm_12v0: fixedregulator-evm12v0 {
@@ -107,6 +109,22 @@ transceiver2: can-phy2 {
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
};
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux0 1>;
+ };
+
+ transceiver4: can-phy4 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux1 1>;
+ };
};
&main_pmx0 {
@@ -144,6 +162,20 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_mcan3_pins_default: main-mcan3-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
+ J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
+ >;
+ };
+
+ main_mcan5_pins_default: main-mcan5-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
+ J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
+ >;
+ };
};
&wkup_pmx0 {
@@ -309,3 +341,17 @@ &mcu_mcan1 {
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
};
+
+&main_mcan3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan3_pins_default>;
+ phys = <&transceiver3>;
+};
+
+&main_mcan5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_pins_default>;
+ phys = <&transceiver4>;
+};
@@ -31,6 +31,18 @@ secure_ddr: optee@9e800000 {
};
};
+ mux0: mux-controller0 {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ mux1: mux-controller1 {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
+ };
+
transceiver0: can-phy0 {
/* standby pin has been grounded by default */
compatible = "ti,tcan1042";