Message ID | e63d1b9404594f12847b1ccb0ad81bbb@tachyum.com |
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State | Unresolved |
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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id b14-20020a1709062b4e00b00988a4c7313fsi942635ejg.269.2023.06.19.03.33.38 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 03:33:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=y1kicfzJ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 566E13858D32 for <ouuuleilei@gmail.com>; Mon, 19 Jun 2023 10:33:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 566E13858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687170817; bh=an4PO3i4uMztE5Aj6tsgeYTAWoWf229eubQuxx5Fq00=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=y1kicfzJjZ8nyCyoHvx7s6tRzhTtfhRVkRZoirmbKBbyXYUu2MJJk/W1eVgNwNn5b MaQay6QmPmC1sKn5jrj0wA6e/nTlW199BaYmxqsNo3FGrJ8Ye1JqqLH+qTGzbPqVuV KiTH+y8M/DgevUdncxw+72vfnlvMfcccyutglgCY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mxa.tachyum.com (mxa.tachyum.com [50.229.46.153]) by sourceware.org (Postfix) with ESMTPS id C1F383858D28 for <gcc-patches@gcc.gnu.org>; Mon, 19 Jun 2023 10:32:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C1F383858D28 X-Virus-Scanned: by SpamTitan at tachyum.com To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org> Subject: [PATCH] Do not allow "x + 0.0" to "x" optimization with -fsignaling-nans Thread-Topic: [PATCH] Do not allow "x + 0.0" to "x" optimization with -fsignaling-nans Thread-Index: AQHZophl7DQKZR/MWEOjFmoa954OUw== Date: Mon, 19 Jun 2023 10:32:41 +0000 Message-ID: <e63d1b9404594f12847b1ccb0ad81bbb@tachyum.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_STY_INVIS_DIRECT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: Toru Kisuki via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Toru Kisuki <tkisuki@tachyum.com> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769126828749673842?= X-GMAIL-MSGID: =?utf-8?q?1769126828749673842?= |
Series |
Do not allow "x + 0.0" to "x" optimization with -fsignaling-nans
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Checks
Context | Check | Description |
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snail/gcc-patch-check | warning | Git am fail log |
Commit Message
Toru Kisuki
June 19, 2023, 10:32 a.m. UTC
Hi, With -O3 -fsignaling-nans -fno-signed-zeros, compiler should not simplify 'x + 0.0' to 'x'. GCC Bugzilla : Bug 110305 gcc/ChangeLog: 2023-06-19 Toru Kisuki <tkisuki@tachyum.com> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): --- gcc/simplify-rtx.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.38.1
Comments
On Mon, Jun 19, 2023 at 12:33 PM Toru Kisuki via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Hi, > > > With -O3 -fsignaling-nans -fno-signed-zeros, compiler should not simplify 'x + 0.0' to 'x'. > OK if you bootstrapped / tested this change. Thanks, Richard. > GCC Bugzilla : Bug 110305 > > > gcc/ChangeLog: > > 2023-06-19 Toru Kisuki <tkisuki@tachyum.com> > > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): > > --- > gcc/simplify-rtx.cc | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc > index e152918b0f1..cc96b36ad4e 100644 > --- a/gcc/simplify-rtx.cc > +++ b/gcc/simplify-rtx.cc > @@ -2698,7 +2698,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, > when x is NaN, infinite, or finite and nonzero. They aren't > when x is -0 and the rounding mode is not towards -infinity, > since (-0) + 0 is then 0. */ > - if (!HONOR_SIGNED_ZEROS (mode) && trueop1 == CONST0_RTX (mode)) > + if (!HONOR_SIGNED_ZEROS (mode) && !HONOR_SNANS (mode) > + && trueop1 == CONST0_RTX (mode)) > return op0; > > /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These > -- > 2.38.1 >
On 6/19/23 05:41, Richard Biener via Gcc-patches wrote: > On Mon, Jun 19, 2023 at 12:33 PM Toru Kisuki via Gcc-patches > <gcc-patches@gcc.gnu.org> wrote: >> >> Hi, >> >> >> With -O3 -fsignaling-nans -fno-signed-zeros, compiler should not simplify 'x + 0.0' to 'x'. >> > > OK if you bootstrapped / tested this change. I'm suspect Toru doesn't have write access. So I went ahead and did and x86 bootstrap & regression test which passed. The ChangeLog entry needed fleshing out a bit and fixed a minor whitespace problem in the patch itself. Pushed to the trunk. jeff
Hi Jeff, Thank you for taking care of it. Toru ________________________________ From: Jeff Law <jeffreyalaw@gmail.com> Sent: Monday, June 19, 2023 7:55 PM To: Richard Biener; Toru Kisuki Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] Do not allow "x + 0.0" to "x" optimization with -fsignaling-nans [EXTERNAL] Caution: This email originated from outside of the organization. On 6/19/23 05:41, Richard Biener via Gcc-patches wrote: > On Mon, Jun 19, 2023 at 12:33 PM Toru Kisuki via Gcc-patches > <gcc-patches@gcc.gnu.org> wrote: >> >> Hi, >> >> >> With -O3 -fsignaling-nans -fno-signed-zeros, compiler should not simplify 'x + 0.0' to 'x'. >> > > OK if you bootstrapped / tested this change. I'm suspect Toru doesn't have write access. So I went ahead and did and x86 bootstrap & regression test which passed. The ChangeLog entry needed fleshing out a bit and fixed a minor whitespace problem in the patch itself. Pushed to the trunk. jeff
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index e152918b0f1..cc96b36ad4e 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -2698,7 +2698,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, when x is NaN, infinite, or finite and nonzero. They aren't when x is -0 and the rounding mode is not towards -infinity, since (-0) + 0 is then 0. */ - if (!HONOR_SIGNED_ZEROS (mode) && trueop1 == CONST0_RTX (mode)) + if (!HONOR_SIGNED_ZEROS (mode) && !HONOR_SNANS (mode) + && trueop1 == CONST0_RTX (mode)) return op0; /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These