Message ID | 20230223-topic-gmuwrapper-v8-18-69c68206609e@linaro.org |
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State | New |
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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id c16-20020ac25310000000b004f2532cfbc1sm4700lfh.81.2023.05.29.06.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 06:52:51 -0700 (PDT) From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Mon, 29 May 2023 15:52:37 +0200 Subject: [PATCH v8 18/18] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230223-topic-gmuwrapper-v8-18-69c68206609e@linaro.org> References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> To: Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Akhil P Oommen <quic_akhilpo@quicinc.com>, Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark <robdclark@chromium.org>, Marijn Suijten <marijn.suijten@somainline.org>, Konrad Dybcio <konrad.dybcio@linaro.org> X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685368343; l=1852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XyERlWDTsfWZFtKFZysYLOHv2ihqt9U+AK25cPIEZ8I=; b=2n8OuzD0JlvWdAYJLyaK9eKey1cglmNCSfu2QjRZowbgEZbyhz4HvTwrDp0kby9LRkmISLbjr Kcr2krpAbHsBJvpoNGqk/mYX4QT+h2FMVRaFTxDXcCH1aHeS+I5R/H0 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767237653771630560?= X-GMAIL-MSGID: =?utf-8?q?1767237653771630560?= |
Series |
GMU-less A6xx support (A610, A619_holi)
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Commit Message
Konrad Dybcio
May 29, 2023, 1:52 p.m. UTC
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
Comments
On Mon, May 29, 2023 at 03:52:37PM +0200, Konrad Dybcio wrote: > > A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 > (trinket) and SM6225 (khaje). Trinket does not support speed binning > (only a single SKU exists) and we don't yet support khaje upstream. > Hence, add a fuse mapping table for bengal to allow for per-chip > frequency limiting. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index d046af5f6de2..c304fa118cff 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -2098,6 +2098,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > return progress; > } > > +static u32 a610_get_speed_bin(u32 fuse) > +{ > + /* > + * There are (at least) three SoCs implementing A610: SM6125 (trinket), > + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, > + * as only a single SKU exists and we don't support khaje upstream yet. > + * Hence, this matching table is only valid for bengal and can be easily > + * expanded if need be. > + */ > + > + if (fuse == 0) > + return 0; > + else if (fuse == 206) > + return 1; > + else if (fuse == 200) > + return 2; > + else if (fuse == 157) > + return 3; > + else if (fuse == 127) > + return 4; > + > + return UINT_MAX; > +} > + > static u32 a618_get_speed_bin(u32 fuse) > { > if (fuse == 0) > @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 > { > u32 val = UINT_MAX; > > + if (adreno_is_a610(adreno_gpu)) > + val = a610_get_speed_bin(fuse); > + Didn't you update here to convert to 'else if' in one of the earlier patches?? Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> -Akhil. > if (adreno_is_a618(adreno_gpu)) > val = a618_get_speed_bin(fuse); > > > -- > 2.40.1 >
On 14.06.2023 22:18, Akhil P Oommen wrote: > On Mon, May 29, 2023 at 03:52:37PM +0200, Konrad Dybcio wrote: >> >> A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 >> (trinket) and SM6225 (khaje). Trinket does not support speed binning >> (only a single SKU exists) and we don't yet support khaje upstream. >> Hence, add a fuse mapping table for bengal to allow for per-chip >> frequency limiting. >> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index d046af5f6de2..c304fa118cff 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -2098,6 +2098,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) >> return progress; >> } >> >> +static u32 a610_get_speed_bin(u32 fuse) >> +{ >> + /* >> + * There are (at least) three SoCs implementing A610: SM6125 (trinket), >> + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, >> + * as only a single SKU exists and we don't support khaje upstream yet. >> + * Hence, this matching table is only valid for bengal and can be easily >> + * expanded if need be. >> + */ >> + >> + if (fuse == 0) >> + return 0; >> + else if (fuse == 206) >> + return 1; >> + else if (fuse == 200) >> + return 2; >> + else if (fuse == 157) >> + return 3; >> + else if (fuse == 127) >> + return 4; >> + >> + return UINT_MAX; >> +} >> + >> static u32 a618_get_speed_bin(u32 fuse) >> { >> if (fuse == 0) >> @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 >> { >> u32 val = UINT_MAX; >> >> + if (adreno_is_a610(adreno_gpu)) >> + val = a610_get_speed_bin(fuse); >> + > > Didn't you update here to convert to 'else if' in one of the earlier > patches?? Right, missed this one! Konrad > > Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > -Akhil. >> if (adreno_is_a618(adreno_gpu)) >> val = a618_get_speed_bin(fuse); >> >> >> -- >> 2.40.1 >>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d046af5f6de2..c304fa118cff 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2098,6 +2098,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse == 0) + return 0; + else if (fuse == 206) + return 1; + else if (fuse == 200) + return 2; + else if (fuse == 157) + return 3; + else if (fuse == 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 { u32 val = UINT_MAX; + if (adreno_is_a610(adreno_gpu)) + val = a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse);