Message ID | 20230603200243.243878-16-varshini.rajendran@microchip.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p6-20020a622906000000b0064feff26183si2895867pfp.3.2023.06.03.13.27.27; Sat, 03 Jun 2023 13:27:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=z5dHuobx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230508AbjFCUIE (ORCPT <rfc822;stefanalexe802@gmail.com> + 99 others); Sat, 3 Jun 2023 16:08:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230345AbjFCUHx (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Sat, 3 Jun 2023 16:07:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9253E7A; Sat, 3 Jun 2023 13:07:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822846; x=1717358846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kR+GAFxGqayegRnGgFCafROzzdAvlW1/3P/cmAH1gx4=; b=z5dHuobx+LF8bCDK/MmJYQ4T3Bv8jl/fz/2FWfLYw6mr74fC9vRcN2Hy gj93XlBFZr6dYUxyGGq2m6zSi4vNMRFmYqDQ0DERjFOuulYEUczQiTxMW 3Rshp+05gklZU4bDI6sahydpCYLodcHA4h9k5lcHcTW8OobYTNQ8LrZ1f a+enyFoVe16881zPCMwWPptx/N/6MBOjm+J3yusG/KZrNh/XXAzbiKbk3 1BU4bQqlYaIBVW7ZRo53QhhuLwTDnJXCycoysF1klwZvcVcV54V+GAimr qKJiFp0Kmxxc/1rmJCC/JxxL39GS6IiOg5oNm2PmnDgt/m+kdkyvMU37C A==; X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="214485477" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:06:23 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:06:22 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:06:10 -0700 From: Varshini Rajendran <varshini.rajendran@microchip.com> To: <tglx@linutronix.de>, <maz@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <claudiu.beznea@microchip.com>, <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>, <gregkh@linuxfoundation.org>, <linux@armlinux.org.uk>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <sre@kernel.org>, <broonie@kernel.org>, <varshini.rajendran@microchip.com>, <arnd@arndb.de>, <gregory.clement@bootlin.com>, <sudeep.holla@arm.com>, <balamanikandan.gunasundar@microchip.com>, <mihai.sain@microchip.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <netdev@vger.kernel.org>, <linux-usb@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-pm@vger.kernel.org> CC: <Hari.PrasathGE@microchip.com>, <cristian.birsan@microchip.com>, <durai.manickamkr@microchip.com>, <manikandan.m@microchip.com>, <dharma.b@microchip.com>, <nayabbasha.sayed@microchip.com>, <balakrishnan.s@microchip.com> Subject: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Date: Sun, 4 Jun 2023 01:32:37 +0530 Message-ID: <20230603200243.243878-16-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767714650680936315?= X-GMAIL-MSGID: =?utf-8?q?1767714650680936315?= |
Series |
Add support for sam9x7 SoC family
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Commit Message
Varshini Rajendran
June 3, 2023, 8:02 p.m. UTC
Document the support added for the Advanced interrupt controller(AIC)
chip in the sam9x7 soc family
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
.../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
Hey Varshini, On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: > Document the support added for the Advanced interrupt controller(AIC) > chip in the sam9x7 soc family Please do not add new family based compatibles, but rather use per-soc compatibles instead. Cheers, Conor. > > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> > --- > .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt > index 7079d44bf3ba..2c267a66a3ea 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt > @@ -4,7 +4,7 @@ Required properties: > - compatible: Should be: > - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2", > "sama5d3" or "sama5d4" > - - "microchip,<chip>-aic" where <chip> can be "sam9x60" > + - "microchip,<chip>-aic" where <chip> can be "sam9x60", "sam9x7" > > - interrupt-controller: Identifies the node as an interrupt controller. > - #interrupt-cells: The number of cells to define the interrupts. It should be 3. > -- > 2.25.1 >
On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote: > Hey Varshini, > > On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: > > Document the support added for the Advanced interrupt controller(AIC) > > chip in the sam9x7 soc family > > Please do not add new family based compatibles, but rather use per-soc > compatibles instead. These things leave me penally confused. Afaiu, sam9x60 is a particular SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and sam9x75. It would appear to me that each should have its own compatible, no? > > Cheers, > Conor. > > > > > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> > > --- > > .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt > > index 7079d44bf3ba..2c267a66a3ea 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt > > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt > > @@ -4,7 +4,7 @@ Required properties: > > - compatible: Should be: > > - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2", > > "sama5d3" or "sama5d4" > > - - "microchip,<chip>-aic" where <chip> can be "sam9x60" > > + - "microchip,<chip>-aic" where <chip> can be "sam9x60", "sam9x7" > > > > - interrupt-controller: Identifies the node as an interrupt controller. > > - #interrupt-cells: The number of cells to define the interrupts. It should be 3. > > -- > > 2.25.1 > >
On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote: > On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote: >> Hey Varshini, >> >> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: >> > Document the support added for the Advanced interrupt controller(AIC) >> > chip in the sam9x7 soc family >> >> Please do not add new family based compatibles, but rather use per-soc >> compatibles instead. > > These things leave me penally confused. Afaiu, sam9x60 is a particular > SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and > sam9x75. It would appear to me that each should have its own compatible, > no? I think the usual way this works is that the sam9x7 refers to the SoC design as in what is actually part of the chip, whereas the 70, 72 and 75 models are variants that have a certain subset of the features enabled. If that is the case here, then referring to the on-chip parts by the sam9x7 name makes sense, and this is similar to what we do on TI AM-series chips. There is a remaining risk that a there would be a future sam9x71/73/74/76/... product based on a new chip that uses incompatible devices, but at that point we can still use the more specific model number to identify those without being ambiguous. The same thing can of course happen when a SoC vendor reuses a specific name of a prior product with an update chip that has software visible changes. I'd just leave this up to Varshini and the other at91 maintainers here, provided they understand the exact risks. It's different for the parts that are listed as just sam9x60 compatible in the DT, I think those clearly need to have sam9x7 in the compatible list, but could have the sam9x60 identifier as a fallback if the hardware is compatible. Arnd
On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote: > On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote: > > On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote: > >> Hey Varshini, > >> > >> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: > >> > Document the support added for the Advanced interrupt controller(AIC) > >> > chip in the sam9x7 soc family > >> > >> Please do not add new family based compatibles, but rather use per-soc > >> compatibles instead. > > > > These things leave me penally confused. Afaiu, sam9x60 is a particular s/penally/perennially/ > > SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and > > sam9x75. It would appear to me that each should have its own compatible, > > no? > > I think the usual way this works is that the sam9x7 refers to the > SoC design as in what is actually part of the chip, whereas the 70, > 72 and 75 models are variants that have a certain subset of the > features enabled. > > If that is the case here, then referring to the on-chip parts by > the sam9x7 name makes sense, and this is similar to what we do > on TI AM-series chips. If it is the case that what differentiates them is having bits chopped off, and there's no implementation differences that seems fair. > There is a remaining risk that a there would be a future > sam9x71/73/74/76/... product based on a new chip that uses > incompatible devices, but at that point we can still use the > more specific model number to identify those without being > ambiguous. The same thing can of course happen when a SoC > vendor reuses a specific name of a prior product with an update > chip that has software visible changes. > > I'd just leave this up to Varshini and the other at91 maintainers > here, provided they understand the exact risks. Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use the "0" model as the compatible (like the 9x60 did) or have "random" things been done so far? > It's different for the parts that are listed as just sam9x60 > compatible in the DT, I think those clearly need to have sam9x7 > in the compatible list, but could have the sam9x60 identifier > as a fallback if the hardware is compatible. Aye.
Arnd, Conor, On 04/06/2023 at 23:08, Conor Dooley wrote: > On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote: >> On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote: >>> On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote: >>>> Hey Varshini, >>>> >>>> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: >>>>> Document the support added for the Advanced interrupt controller(AIC) >>>>> chip in the sam9x7 soc family >>>> Please do not add new family based compatibles, but rather use per-soc >>>> compatibles instead. >>> These things leave me penally confused. Afaiu, sam9x60 is a particular > s/penally/perennially/ > >>> SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and >>> sam9x75. It would appear to me that each should have its own compatible, >>> no? >> I think the usual way this works is that the sam9x7 refers to the >> SoC design as in what is actually part of the chip, whereas the 70, >> 72 and 75 models are variants that have a certain subset of the >> features enabled. Yes, That's the case. >> If that is the case here, then referring to the on-chip parts by >> the sam9x7 name makes sense, and this is similar to what we do >> on TI AM-series chips. This is what we did for most of our SoCs families, indeed. > If it is the case that what differentiates them is having bits chopped > off, and there's no implementation differences that seems fair. Ok, thanks. >> There is a remaining risk that a there would be a future >> sam9x71/73/74/76/... product based on a new chip that uses >> incompatible devices, but at that point we can still use the >> more specific model number to identify those without being >> ambiguous. This is exactly what we did for sama5d29 which is not the same silicon vs. the other members of the sama5d2 family. We used the more specify sama5d29 sub-string for describing the changing parts (CAN-FD and Ethernet). >> The same thing can of course happen when a SoC >> vendor reuses a specific name of a prior product with an update >> chip that has software visible changes. >> >> I'd just leave this up to Varshini and the other at91 maintainers >> here, provided they understand the exact risks. Yep, I understand the risk and will try to review the compatibility strings that would need more precise description (maybe PMC or AIC). > Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use > the "0" model as the compatible (like the 9x60 did) or have "random" > things been done so far? sam9x60 was a single SoC, not a member of a "family", so there was no meaning of the "0" here. Moreover, the "0" ones are usually not the subset, if it even exists. So far, we used the silicon string to define the compatibility string, adding a more precise string for hardware of family members that needed it (as mentioned above for sama5d29). >> It's different for the parts that are listed as just sam9x60 >> compatible in the DT, I think those clearly need to have sam9x7 >> in the compatible list, but could have the sam9x60 identifier >> as a fallback if the hardware is compatible. > Aye. Yep, agreed. Thanks for your help. Best regards, Nicolas
On Mon, Jun 05, 2023 at 02:37:16PM +0200, Nicolas Ferre wrote: > Arnd, Conor, > > On 04/06/2023 at 23:08, Conor Dooley wrote: > > On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote: > > > On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote: > > > > On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote: > > > > > Hey Varshini, > > > > > > > > > > On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: > > > > > > Document the support added for the Advanced interrupt controller(AIC) > > > > > > chip in the sam9x7 soc family > > > > > Please do not add new family based compatibles, but rather use per-soc > > > > > compatibles instead. > > > > These things leave me penally confused. Afaiu, sam9x60 is a particular > > s/penally/perennially/ > > > > > > SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and > > > > sam9x75. It would appear to me that each should have its own compatible, > > > > no? > > > I think the usual way this works is that the sam9x7 refers to the > > > SoC design as in what is actually part of the chip, whereas the 70, > > > 72 and 75 models are variants that have a certain subset of the > > > features enabled. > > Yes, That's the case. > > > If that is the case here, then referring to the on-chip parts by > > > the sam9x7 name makes sense, and this is similar to what we do > > > on TI AM-series chips. > > This is what we did for most of our SoCs families, indeed. > > > If it is the case that what differentiates them is having bits chopped > > off, and there's no implementation differences that seems fair. > > Ok, thanks. > > > > There is a remaining risk that a there would be a future > > > sam9x71/73/74/76/... product based on a new chip that uses > > > incompatible devices, but at that point we can still use the > > > more specific model number to identify those without being > > > ambiguous. > > This is exactly what we did for sama5d29 which is not the same silicon vs. > the other members of the sama5d2 family. We used the more specify sama5d29 > sub-string for describing the changing parts (CAN-FD and Ethernet). > > > > The same thing can of course happen when a SoC > > > vendor reuses a specific name of a prior product with an update > > > chip that has software visible changes. > > > > > > I'd just leave this up to Varshini and the other at91 maintainers > > > here, provided they understand the exact risks. > > Yep, I understand the risk and will try to review the compatibility strings > that would need more precise description (maybe PMC or AIC). > > > Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use > > the "0" model as the compatible (like the 9x60 did) or have "random" > > things been done so far? > > sam9x60 was a single SoC, not a member of a "family", so there was no > meaning of the "0" here. Moreover, the "0" ones are usually not the subset, > if it even exists. > So far, we used the silicon string to define the compatibility string, > adding a more precise string for hardware of family members that needed it > (as mentioned above for sama5d29). > > > > It's different for the parts that are listed as just sam9x60 > > > compatible in the DT, I think those clearly need to have sam9x7 > > > in the compatible list, but could have the sam9x60 identifier > > > as a fallback if the hardware is compatible. > > Aye. > > Yep, agreed. Can we convert this binding to schema so all this is perfectly clear what's valid or not. Rob
diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 7079d44bf3ba..2c267a66a3ea 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,<chip>-aic" where <chip> can be "sam9x60" + - "microchip,<chip>-aic" where <chip> can be "sam9x60", "sam9x7" - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It should be 3.